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| HMS39C7092 Embedded Flash MCU Specification Ver 1.0 System IC SBU, SP BU MCU Business Division, Flash Team Flash MCU(HMS39C7092) Released : February. 2001 ARM(R) is trademark of Advanced RISC Machine Ltd. ARM7TDMI is designed by ARM Ltd. The information contained herein is subject to change without notice. The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by Hynix for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Hynix or others. These Hynix products are intended for usage in general electronic equipment (office equipment, communication equipment, measuring equipment, domestic electrification, etc.). Please make sure that you consult with us before you use these Hynix products in equipment which require high quality and / or reliability, and in equipment which could have major impact to the welfare of human life (atomic energy control, airplane, spaceship, traffic signal, combustion control, all types of safety devices, etc.). Hynix cannot accept liability to any damage which may occur in case these Hynix products were used in th e mentioned equipment without prior consultation with Hynix. Copyright 2000 Hynix Semiconductor, Inc. All Rights Reserved 2 Preliminary Flash MCU(HMS39C7092) Contents Chapter 1........................................................................................................................... 13 Introduction ................................................................................................................. 13 1.1 General Description................................................................................ 14 1.2 Feature.................................................................................................. 15 1.3 Pin Descriptions ..................................................................................... 16 1.4 Operation Mode description .................................................................... 21 1.5 Memory Map.......................................................................................... 25 Chapter 2........................................................................................................................... 27 ARM7TDMI Core ......................................................................................................... 27 2.1 General Description................................................................................ 28 2.2 Feature.................................................................................................. 28 2.3 Core Block Diagram ............................................................................... 29 2.4 Instruction Set ........................................................................................ 30 2.4.1 ARM Instruction .................................................................................. 30 2.4.2 THUMB Instruction.............................................................................. 33 2.4.3 The Program Status Registers ............................................................. 36 2.4.3.1 The condition code flags ............................................................ 37 2.4.3.2 The control bits.......................................................................... 37 2.4.4 ARM pseudo-instructions ..................................................................... 39 2.4.5 THUMB pseudo-instructions ................................................................ 43 Chapter 3........................................................................................................................... 47 BUS Controller ............................................................................................................ 47 3.1 Overview ............................................................................................... 48 3.1.1 Features ............................................................................................. 48 3.1.2 Pin Configuration................................................................................. 49 3.2 Bus Controller Registers ......................................................................... 50 3.2.1 Configuration Registers ....................................................................... 51 3.3 Operation .............................................................................................. 52 3.3.1 Area Division ...................................................................................... 52 3.3.2 Area Division ...................................................................................... 53 3.3.3 Chip Select Signals ............................................................................. 53 3.4 Basic Bus Interface ................................................................................ 54 3.4.1 Overview ............................................................................................ 54 3.4.2 Byte Lane Write Control ....................................................................... 54 3.4.3 Basic Bus Control Signal Timing........................................................... 56 3.4.4 Wait Control ........................................................................................ 62 3.4.5 Bus Arbiter.......................................................................................... 63 Chapter 4........................................................................................................................... 65 MCU Controller ........................................................................................................... 65 4.1 General Description................................................................................ 66 4.2 Pin Function Description......................................................................... 66 4.3 Register Description ............................................................................. 67 4.3.1 Register Memory Map ......................................................................... 67 4.3.2 PINMUX Register ................................................................................ 68 4.3.3 MCU Device Code Register (0x0900_002C Read Only) ...................... 72 Preliminary 3 Flash MCU(HMS39C7092) Chapter 5........................................................................................................................... 73 Power Management Unit.............................................................................................. 73 5.1 General Description................................................................................ 74 5.2 Operation Modes.................................................................................... 75 5.2.1 Introduction......................................................................................... 75 5.2.2 Reset and Operation Modes ................................................................ 75 5.3 Power Management Unit Register Map.................................................... 77 5.4 Register Description ............................................................................... 78 5.5 Signal Timing Diagram............................................................................ 81 5.5.1 Power on Reset .................................................................................. 81 5.5.2 Watch Dog Timer Overflow .................................................................. 81 5.5.3 Soft-Reset .......................................................................................... 82 Chapter 6........................................................................................................................... 83 The Interrupt Controller................................................................................................ 83 6.1 About the Interrupt controller ................................................................... 84 6.1.1 Interrupt sources ................................................................................. 85 6.1.2 Interrupt Control .................................................................................. 85 6.2 Interrupt Controller Registers .................................................................. 87 Chapter 7........................................................................................................................... 91 Watchdog Timer .......................................................................................................... 91 7.1 General Description................................................................................ 92 7.2 Watchdog Timer Introduction................................................................... 93 7.3 Watchdog Timer Operation ..................................................................... 94 7.3.1 Timing of Setting and Clearing the Overflow Flag .................................. 95 7.4 Watchdog Timer Memory Map................................................................. 96 7.5 Watchdog Timer Register Descriptions .................................................... 97 7.6 Examples of Register Setting ................................................................ 100 7.6.1 Interval Timer Mode......................................................................... 100 7.6.2 Watchdog Timer Mode with Internal Reset Disable .............................. 101 7.6.3 Watchdog Timer Mode with Power-on Reset ....................................... 102 7.6.4 Watchdog Timer Mode with Manual Reset .......................................... 103 Chapter 8......................................................................................................................... 105 The General Purpose Timer ....................................................................................... 105 8.1 About the General Purpose Timer Unit................................................... 106 8.1.1 General Purpose Timer Unit Introduction ............................................ 107 8.2 General Purpose Timer Unit Memory Map ............................................. 108 8.2.1 Register Assignment ......................................................................... 108 8.2.2 General Purpose Timer Unit Register Descriptions .............................. 109 8.2.2.1 Timer Global Control Registers ................................................. 109 8.2.2.2 Timer Channel Control Registers .............................................. 110 8.3 General Purpose Timer Unit Operation .................................................. 114 8.3.1 Free Running Mode........................................................................... 115 8.3.2 Compare Match Mode ....................................................................... 117 8.3.3 Input Capture Mode........................................................................... 119 8.3.4 Synchronized Clear and Write Mode................................................... 120 8.3.5 PWM Mode....................................................................................... 121 8.3.5.1 PWM Mode Operation ............................................................. 121 Chapter 9......................................................................................................................... 125 UART (Universal Asynchronous Receiver/Transmitter)................................................. 125 4 Preliminary Flash MCU(HMS39C7092) General Description.............................................................................. 126 Features .............................................................................................. 127 Signal Description ................................................................................ 127 Internal Block Diagram ......................................................................... 128 Registers Description ........................................................................... 129 UART Operations ................................................................................. 140 9.6.1 FIFO Interrupt Mode Operation .......................................................... 140 9.6.2 FIFO Polled Mode Operation ............................................................. 141 9.7 Register Summary................................................................................ 142 Chapter 10. ...................................................................................................................... 143 GPIO (General Purpose Input Output) ........................................................................ 143 10.1 General Description.............................................................................. 144 10.2 GPIO Registers .................................................................................... 145 10.2.1 Register Memory Map...................................................................... 145 10.3.1 Register Description ........................................................................ 146 10.3 Functional Description .......................................................................... 147 Chapter 11 ....................................................................................................................... 149 On-Chip SRAM ......................................................................................................... 149 11.1 General Description.............................................................................. 150 11.2 Function Description............................................................................. 150 Chapter 12 ....................................................................................................................... 151 On-chip Flash Memory ............................................................................................... 151 12.1 General Description.............................................................................. 152 12.2 Features .............................................................................................. 152 12.3 Block Diagram ..................................................................................... 154 12.4 Flash Memory Register Description ....................................................... 156 12.5 On-Board Programming Mode .............................................................. 161 12.5.1 Boot Mode ..................................................................................... 161 12.5.2 User Program Mode ....................................................................... 164 12.6 Flash Memory Programming/Erasing ..................................................... 166 12.6.1 Program & Program-Verify Mode ...................................................... 166 12.6.2 Pre-program & Pre-program Verify Mode ......................................... 168 12.6.3 Erase & Erase Verify Mode ............................................................. 170 12.6.4 Erase Algorithm .............................................................................. 172 12.7 Flash Memory PROM Mode .................................................................. 173 12.7.1 PROM Mode Setting ....................................................................... 173 12.7.2 Memory Map .................................................................................. 174 12.7.3 PROM Mode Operation................................................................... 174 12.7.4 Timing Diagram and AC/DC Characteristics ..................................... 175 Chapter 13 ....................................................................................................................... 179 A/D Converter ........................................................................................................... 179 13.1 Overview ............................................................................................. 180 13.1.1 Features ......................................................................................... 180 13.1.2 Pin Configuration ............................................................................. 181 13.2 A/D Converter Registers ....................................................................... 182 13.2.1 Register Descriptions ....................................................................... 182 13.3 Operation ............................................................................................ 185 13.4 Interrupts ............................................................................................. 186 13.5 Usage Notes ........................................................................................ 187 9.1 9.2 9.3 9.4 9.5 9.6 Preliminary 5 Flash MCU(HMS39C7092) 13.6 Example .............................................................................................. 190 Chapter 14 ....................................................................................................................... 191 Electrical Characteristics............................................................................................ 191 14.1 Absolute Maximum Ratings................................................................... 192 14.2 Recommended Operating Conditions: ................................................... 192 14.3 DC Characteristics ............................................................................... 193 14.4 AC Characteristics................................................................................ 194 14.4 AD Conversion characteristics (Preliminary)........................................... 196 14.5 Operational Timing ............................................................................... 197 14.5.1 Clock Timing ..................................................................................... 197 14.5.2 Reset Timing .................................................................................... 197 14.5.3 Bus Timing ....................................................................................... 198 Appendix A-1 A-2 Peripheral Setting & Flash memory control Examples Package Dimension 6 Preliminary Flash MCU(HMS39C7092) Figures Figure 1.1 Package Outline........................................................................................ 14 Figure 1.2 HMS39C7092 Block Diagram .................................................................... 15 Figure 1.3 HMS39C7092 Memory Map....................................................................... 25 Figure 1.4 Memory Map of Mode 3............................................................................. 25 Figure 1.5 Memory Map of when Mode 4 and Mode 5 ................................................. 26 Figure 1.6 Memory Map of Mode 6 and Mode 7 .......................................................... 26 Figure 2.1 ARM7TDMI Core Block Diagram ................................................................ 29 Figure 2.2 ARM instruction set formats ....................................................................... 30 Figure 2.3 Register Organization in ARM state............................................................ 32 Figure 2.4 THUMB instruction set formats................................................................... 33 Figure 2.5 Register Organization in THUMB state ....................................................... 35 Figure 2.6 Mapping of THUMB state registers onto ARM state registers. ...................... 35 Figure 2.7 Program status register format ................................................................... 36 Figure 3.1 Block Diagram of the Bus Controller ........................................................... 48 Figure 3.2 Access Area Map for Each Operating Mode................................................ 52 Figure 3.3 Access Size and Data Alignment Control (8-Bit Access Area) ...................... 54 Figure 3.4 Access Size and Data Alignment Control (16-Bit Access Area) .................... 55 Figure 3.5 Bus Control Signal Write Timing for 16-Bit, 1-Wait (Word Access) ................ 56 Figure 3.6 Bus Control Signal Read Timing for 16-Bit, 1-Wait (Word Access)................ 56 Figure 3.7 Bus Control Signal Write Timing for 16-Bit, 1-Wait (Half-word Access).......... 57 Figure 3.8 Bus Control Signal Read Timing for 16-Bit, 1-Wait (Half-word Access).......... 57 Figure 3.9 Bus Control Signal Write Timing for 16-Bit, 1-Wait (Byte Access).................. 58 Figure 3.10 Bus Control Signal Read Timing for 16-Bit, 1-Wait (Byte Access)................ 58 Figure 3.11 Bus Control Signal Write Timing for 16-Bit, 2-Wait (Word Access)............... 59 Figure 3.12 Bus Control Signal Read Timing for 16-Bit, 2-Wait (Word Access) .............. 59 Figure 3.13 Bus Control Signal Write Timing for 16-Bit, 2-Wait (Half-Word Access)........ 60 Figure 3.14 Bus Control Signal Read Timing for 16-Bit, 2-Wait (Half-Word Access) ....... 60 Figure 3.15 Bus Control Signal Write Timing for 16-Bit, 2-Wait (Byte Access)................ 61 Figure 3.16 Bus Control Signal Read Timing for 16-Bit, 2-Wait (Byte Access)................ 61 Figure 3.17 Example of Wait State Insertion Timing. .................................................... 62 Figure 3.18 Example of External Bus Master Operation............................................... 64 Figure 5.1 PMU Block Diagram .................................................................................. 74 Figure 5.2 Reset and Power Management State Machine. ........................................... 76 Figure 5.3 Power on Reset Timing Diagram ................................................................ 81 Figure 5.4 Watch Dog Timer Overflow Timing Diagram ................................................ 81 Figure 5.5 Soft Reset (from WDT) Timing Diagram ...................................................... 82 Figure 5.6 Soft Reset (from PMU) Timing Diagram ...................................................... 82 Figure 6.1 Interrupt Control Flow Diagram .................................................................. 84 Figure 7.1 Watchdog Timer Module Block Diagram ..................................................... 92 Figure 7.2 Operation in the Watchdog Timer Mode ...................................................... 94 Figure 7.3 Operation in the Interval Timer Mode .......................................................... 95 Figure 7.4 Interrupt Clear in the Interval Timer Mode ................................................. 100 Figure 7.5 Interrupt Clear in the Watchdog Timer Mode with Reset Disable................. 101 Figure 7.6 Interrupt Clear in the Watchdog Timer Mode with Power-on Reset.............. 102 Figure 7.7 Interrupt Clear in the Watchdog Timer Mode with Manual Reset ................. 103 Figure 8.1 General-purpose Timer Unit Module Block Diagram .................................. 106 Preliminary 7 Flash MCU(HMS39C7092) Figure 8.2 Free-Running Counter Operation ............................................................. 115 Figure 8.3 Periodic Counter Operation...................................................................... 116 Figure 8.4 Example of 0 Output/1 Output .................................................................. 117 Figure 8.5 Example of Toggle Output ........................................................................ 118 Figure 8.6 Compare Match Signal Output Timing ...................................................... 118 Figure 8.7 Input Capture Operation .......................................................................... 119 Figure 8.8 Synchronized Operation Example ............................................................ 120 Figure 8.9 PWM Mode Operation Example 1 ............................................................ 121 Figure 8.10 PWM Mode Operation Example 2........................................................... 122 Figure 8.11 Reset-Synchronized PWM Mode Operation Example............................... 123 Figure 9.1 TOP BLOCK Diagram ............................................................................. 126 Figure 9.2 Internal UART Diagram ........................................................................... 128 Figure 10.1 GPIO Block Diagram and PADS Connections(example for Port A and Port B) ......................................................................................................................... 144 Figure 12.1 Block Diagram of Flash Memory ............................................................. 154 Figure 12.2 System Configuration When Using On-Board Boot Mode ......................... 161 Figure 12.3 Boot Mode Execution Procedure ............................................................ 162 Figure 12.4 User Mode Execution Procedure............................................................ 164 Figure 12.5 Flash Program & Program Verify Sequence............................................ 167 Figure 12.6 Flash Pre-program & Pre-program Verify Sequence ................................ 169 Figure 12.7 Flash Erase & Erase Verify Sequence .................................................... 171 Figure 12.8 Flash Erase Algorithm ........................................................................... 172 Figure 12.9 Timing Diagram of Read ........................................................................ 175 Figure 12.10 Timing Diagram of Pre-Program/Program ............................................. 176 Figure 12.11 Timing Diagram of Erase...................................................................... 176 Figure 12.12 Timing Diagram of Pre-Program/Program Verify .................................... 177 Figure 12.13 Timing Diagram of Erase Verify ............................................................ 177 Figure 13.1 Block Diagram of A/D Converter............................................................. 180 Figure 13.2 A/D converter Operation ........................................................................ 185 Figure 13.3 Example of Analog Input Circuit ............................................................. 188 Figure 13.4 A/D Converter Accuracy Definitions (1)................................................... 188 Figure 13.5 A/D Converter Accuracy Definitions (2)................................................... 189 Figure 14.1 The settling time of the crystal oscillator.................................................. 197 Figure 14.2 Reset Input Timing ................................................................................ 197 Figure 14.3 The Write Timing Diagram of the Bus Controller ...................................... 198 Figure 14.4 The Read Timing Diagram of the Bus Controller ...................................... 198 Figure 14.5 Basic Bus Cycle with External Wait State................................................ 199 Figure 14.6 Bus Release Mode Timing ..................................................................... 199 8 Preliminary Flash MCU(HMS39C7092) Tables Table 1.1 Pin Descriptions ......................................................................................... 16 Table 1.1 Pin Descriptions (Continued) ....................................................................... 17 Table 1.1 Pin Descriptions (Continued) ....................................................................... 18 Table 1.1 Pin Descriptions (Continued) ....................................................................... 19 Table 1.1 Pin Descriptions (Continued) ....................................................................... 20 Table 1.2 HMS39C7092 Operation modes .................................................................. 21 Table 1.3 Pin assignment by mode............................................................................. 22 Table 1.3 Pin assignment by mode (continued) ........................................................... 23 Table 1.3 Pin assignment by mode (continued) ........................................................... 24 Table 2.1 The ARM Instruction set .............................................................................. 31 Table 2.2 THUMB instruction set opcodes ................................................................... 34 Table 2.3 Condition code summary ............................................................................. 36 Table 2.4 PSR mode bit values .................................................................................. 38 Table 3.1 Bus Controller Pins ..................................................................................... 49 Table 3.2 BUS Controller Register Map....................................................................... 50 Table 3.3 Byte Lane condition by XA[0] ....................................................................... 55 Table 4.1 Pin Function Descriptions ............................................................................ 66 Table 4.2 Memory map of the MCU Controller ............................................................. 67 Table 4.3 MCU Controller Initial values in each mode .................................................. 67 Table 5.1 Register Map of the PMU ............................................................................ 77 Table 6.1 Interrupt Controller Default Setting Value...................................................... 85 Table 6.2 Memory Map of the Interrupt Controller ........................................................ 87 Table 6.3 Interrupt Source Trigger Mode..................................................................... 88 Table 7.1 Memory Map of the Watchdog Timer APB Peripheral .................................... 96 Table 7.2 Internal Counter Clock Sources (SYSCLK = 40 MHz).................................... 98 Table 8.1 Timer Global Control Register Map ............................................................ 108 Table 8.2 Timer Channel Control Register Map ......................................................... 108 Table 8.3 Timer Channel Starting Address ................................................................ 108 Table 9.1 Signal Descriptions ................................................................................... 127 Table 9.2 UART Register Address Map (0x1500 in UART1) ....................................... 129 Table 9.3 UART Register Reset Values ..................................................................... 129 Table 9.4a Divisor Values for each Baud rate (CLK=1.8432MHz)................................ 133 Table 9.4b Divisor Values for each Baud rate (CLK=3.6864MHz)................................ 133 Table 9.5 Interrupt Control Functions ........................................................................ 138 Table 9.6 Summary of Registers............................................................................... 142 Table 10.1 GPIO Register Memory Map.................................................................... 145 Table 12.1 Operating mode...................................................................................... 153 Table 12.2 Signal description of Figure 12.1(BUS Interface) ....................................... 155 Table 12.3 Flash Memory Registers.......................................................................... 156 Table 12.4 Control Register...................................................................................... 158 Table 12.5 Erase Block Register............................................................................... 159 Table 12.6 Status & Power Register ......................................................................... 160 Table 12.7 FR_SEL Value for access to internal Register ........................................... 173 Table 12.8 Setting for Register read/write.................................................................. 173 Table 12.9 Erase Block Register............................................................................... 174 Table 12.10 Setting for Flash PROM read/write ......................................................... 175 Preliminary 9 Flash MCU(HMS39C7092) Table Table Table Table Table Table Table Table Table Table Table Table Table Table 12.11 DC Characteristics ................................................................................ 178 12.12 AC Characteristics ................................................................................ 178 13.1 A/D Converter Pins ................................................................................. 181 13.2 Summarizes the A/D converter's registers. ............................................... 182 14.1 Absolute Maximum Ratings - Preliminary -............ 192 14.2 Recommended Operating Conditions - Preliminary- ............. 192 14.3 DC Characteristics - Preliminary- .......... 193 14.4 IO Circuits with pull-ups - Preliminary- ........... 193 14.5 IO Circuits with pull-downs - Preliminary- ............ 193 14.6 Clock Timing - Preliminary-........... 194 14.7 Control Signal Timing - Preliminary- ........... 194 14.8 Bus Timing - Preliminary- .......... 195 14.9 Operating Conditions of the AD Conversion - Preliminary-............. 196 14.10 Electrical characteristics of the AD converter - Preliminary-............. 196 10 Preliminary Flash MCU(HMS39C7092) Preliminary 11 Flash MCU(HMS39C7092) 12 Preliminary Flash MCU(HMS39C7092) Introduction Chapter 1 Introduction Preliminary 13 Introduction 1.1 General Description Flash MCU(HMS39C7092) The 16bit MCU with embedded flash memory for optical storage is the first member of Hynix Micro Electronics 16/32bit MCU Family of high performance microcontroller units (MCUs). This family includes a series of peripherals from which numerous MCUs are assembled. This MCU contains extensive peripherals : 192Kbytes flas h memory, 4K bytes SRAM, 6 channel 16bit Timer, Watch Dog Timer, 2 channel UART, Programmable Priority Interrupt Controller, 81bits PIO, BUS Controller including Chip select logic, which is On-Chip Modular Architecture (using AMBA). A14/P2 6 1 A15/P2 7 2 A16/P5 0 3 A17/P5 1 4 A18/P5 2 5 A19/P5 3 6 VSS 7 nWAIT/P6 0 8 9 nBREQ/P6 1 nBACK/P6 2 0 1 CLKO/P67 nSTBY 2 nRES 3 4 nTRST/P9 7 VSS 5 6 XTALOUT XTALIN 7 VDD 8 nAS/P6 3 9 nRD/P6 4 0 1 nHWR/P6 5 2 nLWR/P6 6 MODE0 3 MODE1 4 MODE2 5 5 5 5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 6 6 7 7 7 7 7 7 A13 /P25 A12 /P24 A11 /P23 A10 /P22 A9/P2 1 A8/P2 0 VSS A7/P1 7 A6/P1 6 A5/P1 5 A4/P1 4 A3/P1 3 A2/P1 2 A1/P1 1 A0/P1 0 VDD D15/P3 7 D14/P3 6 D13/P3 5 D12/P3 4 D11/P3 3 D10/P3 2 D9/P3 1 D8/P3 0 D7/P4 7 14 VDD nCS7/TIOCA3/PB 0 nCS6/TIOCB3/PB 1 nCS5/TIOCA4/PB 2 nCS4/TIOCB4/PB 3 TMS/PB 4 TDO/PB 5 TDI/PB6 TCK/PB 7 0 XP96 1 VSS 2 TxD0/P9 0 3 RxD0/P91 4 TxD1/P9 2 5 RxD1/P93 6 nIRQ 4/P9 4 7 nIRQ 5/P9 5 8D0/P40 9D0/P40 0D2/P42 1D3/P43 2 VSS 3D4/P44 4D5/P45 5D6/P46 1 2 3 4 5 6 7 8 9 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 AVDD AV REF AN 0/P7 0 AN 0/P7 1 AN 0/P7 2 AN 0/P7 3 AN 0/P7 4 VSS TIOCA5/nIRQ 6/P7 6 TIOCB5/nIRQ 7/P7 7 P75 nIRQ0/P8 0 nCS3/nIRQ 1/P81 nCS2/nIRQ 2/P82 nCS1/nIRQ 3/P83 nCS0/P8 4 VSS TCLKA/PA 0 TCLKB/PA 1 TCLKC/TCIOA0/PA2 TCLKD/TCIOB0/PA3 A23/TIOCA1/PA 4 A22/TIOCB1/PA 5 A21/TIOCA2/PA 6 A20/TIOCB2/PA 7 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 HMS39C7092 2001.02 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 Figure 1.1 Package Outline Preliminary Flash MCU(HMS39C7092) 1.2 Feature Introduction * On-Chip Modular Architecture (using AMBA) * Utilizes the ARM7TDMI 32/16bit RISC Family * 192Kbyte flash memory * 4Kbyte internal SRAM * 8/16-bit external Data Bus * Eight Programmable Chip Select Outputs with external wait input * Low Power Consumption using Power Management Unit * Fully static operation : Max. 50MHz * Programmable Priority Interrupt Controller (8 external sources) * Six 16bit Multi Function Timers/Counters for General Purpose Applications * One 8bit Watch Dog Timer (WDT) * Two UARTs (Universal Asynchronous Receiver Transmitter) compatible with 16C550 UART * Programmable Input/Output ports (81-bits) * 100 TQFP Package Max. 50MHz Arbiter Arbiter PMU PMU PIO PIO INTC INTC BUS BUS Controller Controller ARM7TDMI ARM7TDMI ASB (Max. 50MHz) TIC* TIC* APB APB Bridge Bridge WDT WDT TIMER TIMER UART UART SRAM SRAM 4kbyte 4kbyte Flash Memory Flash Memory 192kbyte 192kbyte Multi-Function Pin MUX Multi-Function Pin MUX ADC ADC * TIC : Test Interface Controller Figure 1.2 HMS39C7092 Block Diagram Preliminary 15 Introduction 1.3 PIN 1 2 Flash MCU(HMS39C7092) Pin Descriptions SYMBOL VDD nCS7 TCIOA3 PB0 nCS6 DIR O I/O I/O O I/O I/O O I/O I/O O I/O I/O I I/O O I/O I I/O I I/O I O I/O O I/O O I/O O I/O I I/O I I/O I/O I/O I/O I/O I/O I/O I/O I/O Power Supply 3.3V External Chip Selection Number 7 PWM output, Compare match output of Reg.A and signal capture input of Timer Ch3 General purpose input output of port B bit0 External Chip Selection Number 6 PWM output, Compare match output of Reg.B and signal capture input of Timer Ch3 General purpose input output of port B bit 1 External Chip Selection Number 5 PWM output, Compare match output of Reg.A and signal capture input of Timer Ch4 General purpose input output of port B bit2 External Chip Selection Number 4 PWM output, Compare match output of Reg.B and signal capture input of Timer Ch4 General purpose input output of port B bit3 JTAG Test Mode Selection General purpose input output of port B bit4 JTAG Test Data Output General purpose input output of port B bit5 JTAG Test Data Input General purpose input output of port B bit6 JTAG Test Clock General purpose input output of port B bit7 5Vinput for the use of Programming and Erasing of the Flash Memory Power ground Transmit Data of UART Ch0 General purpose input output of port 9 bit 0 Receive Data of UART Ch0 General purpose input output of port 9 bit 1 Transmit Data of UART Ch1 General purpose input output of port 9 bit 2 Receive Data of UART Ch1 General purpose input output of port 9 bit 3 External Interrupt Request number 4 General purpose input output of port 9 bit 4 External Interrupt Request number 5 General purpose input output of port 9 bit 5 External Data Bus bit 0 General purpose input output or port 4 bit 0 External Data Bus bit 1 General purpose input output or port 4 bit 1 External Data Bus bit 2 General purpose input output or port 4 bit 2 External Data Bus bit 3 General purpose input output or port 4 bit 3 DESCRIPTION Table 1.1 Pin Descriptions 3 TCIOB3 PB1 nCS5 4 TIOCA4 PB2 nCS4 5 TIOCB4 PB3 TMS PB4 TDO PB5 TDI PB6 TCK PB7 TVPPD VSS TxD0 P90 RxD 0 P91 TxD1 P92 RxD 1 P93 nIRQ4 P94 nIRQ5 P95 D0 P40 D1 P41 D2 P42 D3 P43 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 16 Preliminary Flash MCU(HMS39C7092) Table 1.1 Pin Descriptions (Continued) PIN 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SYMBOL VSS D4 P44 D5 P45 D6 P46 D7 P47 D8 P30 D9 P31 D 10 P32 D 11 P33 D 12 P34 D 13 P35 D 14 P36 D 15 P37 VDD A0 P10 A1 P11 A2 P12 A3 P13 A4 P14 A5 P15 A6 P16 A7 P17 VSS A8 P20 A9 P21 A10 P22 DIR I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O I/O O I/O O I/O O I/O O I/O O I/O O I/O O I/O O I/O O I/O O I/O Power ground External Data Bus bit 4 General purpose input output or port 4 bit 4 External Data Bus bit 5 General purpose input output or port 4 bit 5 External Data Bus bit 6 General purpose input output or port 4 bit 6 External Data Bus bit 7 General purpose input output or port 4 bit 7 External Data Bus bit 8 General purpose input output or port 3 bit 0 External Data Bus bit 9 General purpose input output or port 3 bit 1 External Data Bus bit 10 General purpose input output or port 3 bit 2 External Data Bus bit 11 General purpose input output or port 3 bit 3 External Data Bus bit 12 General purpose input output or port 3 bit 4 External Data Bus bit 13 General purpose input output or port 3 bit 5 External Data Bus bit 14 General purpose input output or port 3 bit 6 External Data Bus bit 15 General purpose input out put or port 3 bit 7 Power Supply 3.3V External Address Bus bit 0 General purpose input output or port 1 bit 0 External Address Bus bit 1 General purpose input output or port 1 bit 1 External Address Bus bit 2 General purpose input output or port 1 bit 2 External Address Bus bit 3 General purpose input output or port 1 bit 3 External Address Bus bit 4 General purpose input output or port 1 bit 4 External Address Bus bit 5 General purpose input output or port 1 bit 5 External Address Bus bit 6 General purpose input output or port 1 bit 6 External Address Bus bit 7 General purpose input output or port 1 bit 7 Power ground External Address Bus bit 8 General purpose input output or port 2 bit 0 External Address Bus bit 9 General purpose input output or port 2 bit 1 External Address Bus bit 10 General purpose input output or port 2 bit 2 DESCRIPTION Introduction Preliminary 17 Introduction Table 1.1 Pin Descriptions (Continued) PIN 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 SYMBOL A11 P23 A12 P24 A13 P25 A14 P26 A15 P27 A16 P50 A17 P51 A18 P52 A19 P53 VSS nWAIT P60 nBREQ P61 nBACK P62 CLKO P67 nSTBY nRES nTRST P97 VSS XTALOUT XTALIN VDD nAS P63 nRD P64 nHWR P65 nLWR P66 MODE0 MODE1 MODE2 AVDD AVREF DIR O I/O O I/O O I/O O I/O O I/O O I/O O I/O I I/O O I/O I I/O I I/O I I/O O I/O O I I I/O O I O I/O O I/O O I/O O I/O I I I External Address Bus bit 11 General purpose input output or port 2 bit 3 External Address Bus bit 12 General purpose input output or port 2 bit 4 External Address Bus bit 13 General purpose input output or port 2 bit 5 External Address Bus bit 14 General purpose input output or port 2 bit 6 External Address Bus bit 15 General purpose input output or port 2 bit 7 External Address Bus bit 16 General purpose input output of port 5 bit 0 External Address Bus bit 17 General purpose input output of port 5 bit 1 External Address Bus bit 18 General purpose input output of port 5 bit 2 External Address Bus bit 19 General purpose input output of port 5 bit 3 Power ground External BUS cycle wait signal General purpose input output of port 6 bit 0 External BUS Request General purpose input output of port 6 bit 1 External BUS Acknowledge General purpose input output of port 6 bit 2 BUS Clock Output General purpose input output of port 6 bit 7 Standby mode signal. Power Down mode indicating External Reset input JTAG Test Reset input General purpose input output of port 9 bit 7 Power ground Crystal feedback output Crystal or External Oscillator input Power Supply 3.3V External Address Bus strobe General purpose input output of port 6 bit 3 External Bus Read General purpose input output of port 6 bit 4 External upper 8 bit data bus write General purpose input output of port 6 bit 5 External lower 8 bit data bus write General purpose input output of port 6 bit 6 MODE bit 0 MODE bit 1 MODE bit 2 Analog Power Supply 3.3V ADC Reference Voltage Flash MCU(HMS39C7092) DESCRIPTION 18 Preliminary Flash MCU(HMS39C7092) Table 1.1 Pin Descriptions (Continued) PIN 78 79 80 81 82 83 84 SYMBOL P70 AN 0 P71 AN 1 P72 AN 2 P73 AN 3 P74 AN 4 VSS TIOCA5 nIRQ6 P76 TIOCB5 85 86 87 nIRQ7 P77 P75 nIRQ0 P80 nCS3 88 nIRQ1 P81 nCS2 89 nIRQ2 P82 nCS1 90 nIRQ3 P83 91 92 93 94 nCS0 P84 VSS TCLKA PA0 TCLKB PA1 TCLKC 95 TIOCA0 PA2 TCLKD 96 TIOCB0 PA3 A23 97 TIOCA1 PA4 DIR O I O I O I O I O I I/O I I/O I/O I I/O I/O I I/O O I I/O O I I/O O I I/O O I/O I I/O I I/O I I/O I/O I I/O I/O O I/O I/O General purpose output of port 7 bit 0 ADC Channel 0 input General purpose output of port 7 bit 1 ADC Channel 1 input General purpose output of port 7 bit 2 ADC Channel 2 input General purpose output of port 7 bit 3 ADC Channel 3 input General purpose output of port 7 bit 4 ADC Channel 4 input Power ground DESCRIPTION Introduction PWM output, Compare match output of Reg.A and signal capture input of Timer Ch5 External Interrupt Request number 6 General purpose input output of port 7 bit 6 PWM output, Compare match output of Reg.B and signal capture input of Timer Ch5 External Interrupt Request number 7 General purpose input output of port 7 bit 7 General purpose input output of port 7 bit 5 External Interrupt Request number 0 General purpose input output of port 8 bit 0 External Chip Selection Number 3 External Interrupt Request number 1 General purpose input output of port 8 bit 1 External Chip Selection Number 2 External Interrupt Request number 2 General purpose input output of port 8 bit 2 External Chip Selection Number 1 External Interrupt Request number 3 General purpose input output of port 8 bit 3 External Chip Selection Number 0 General purpose input output of port 8 bit 4 Power ground External timer input clock A General purpose input output of port A bit 0 External timer input clock B General purpose input output of port A bit 1 External timer input clock C PWM output, Compare match output of Reg.A and signal capture input of Timer Ch0 General purpose input output of port A bit 2 External timer input clock D PWM output, Compare match output of Reg.B and signal capture input of Timer Ch0 General purpose input output of port A bit 3 External Address Bus bit 23 PWM output, Compare mat ch output of Reg.A and signal capture input of Timer Ch1 General purpose input output of port A bit 4 Preliminary 19 Introduction Table 1.1 Pin Descriptions (Continued) PIN 98 SYMBOL A22 TIOCB1 PA5 A21 99 TIOCA2 PA6 A20 100 TIOCB2 PA7 DIR O I/O I/O O I/O I/O O I/O I/O External Address Bus bit 22 Flash MCU(HMS39C7092) DESCRIPTION PWM output, Compare match output of Reg.B and signal capture input of Timer Ch1 General purpose input output of port A bit 5 External Address Bus bit 21 PWM output, Compare match output of Reg.A and signal capture input of Timer Ch2 General purpose input output of port A bit 6 External Address Bus bit 20 PWM output, Compare match output of Reg.B and signal capture input of Timer Ch2 General purpose input output of port A bit 7 20 Preliminary Flash MCU(HMS39C7092) 1.4 Operation Mode description Introduction HMS39C7092 is Flash Memory-embedded ARM microcontroller. It has six-operation modes shown in Table 1.2. HMS39C7092 External pin function is changed by setting external MODE pin or configuring the PIN MUX registers. The pin assignment by mode is shown in Table 1.3. Especially changing mode causes memory remap for appropriate mode. Figure 1.3 shows default memory map and the memory maps of respective modes are shown in Figure 1.4, Figure 1.5 and Figure 1.6. The Mode definition is listed as follows: Table 1.2 HMS39C7092 Operation modes MODE 0,1 2 3 4 5 6 7 Reserved for Test External 8-bit data bus with 16MBytes of Address Range External 16-bit data bus with 16MBytes of Address Range Flash-boot mode with 16-bit data bus Flash-boot mode (micro-computer mode) UART-boot mode with 16-bit data bus UART-boot mode (micro-computer mode) MODE DESCRIPTION Preliminary 21 Introduction Table 1.3 Pin assignment by mode PIN MODE 2 External 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 8bit BUS VDD nCS7 nCS6 nCS5 nCS4 TMS TDO TDI TCK TVPPD VSS TxD0 RxD0 TxD1 RxD1 nIRQ4 nIRQ5 D0 D1 D2 D3 VSS D4 D5 D6 D7 P30 P31 P32 P33 P34 P35 P36 P37 VDD A0 A1 A2 A3 A4 MODE 3 External 16bit BUS D8 D9 D10 D11 D12 D13 D14 D15 MODE 4 Flash boot mode with 16bit BUS MODE 6 Flash MCU(HMS39C7092) MODE 5 Flash boot mode (MICOM mode) TIOCA3 TIOCB3 TIOCA4 TIOCB4 P40 P41 P42 P43 P44 P45 P46 P47 P30 P31 P32 P33 P34 P35 P36 P37 P10 P11 P12 P13 P14 MODE 7 UART boot mode (MICOM mode) UART boot mode with 16bit BUS 22 Preliminary Flash MCU(HMS39C7092) Table 1.3 Pin assignment by mode (continued) PIN No. MODE2 External 8bit BUS A5 A6 A7 VSS A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 VSS nWAIT nBREQ nBACK CLKO nSTBY nRES nTRST VSS XTALOUT XTALIN VDD nAS nRD nHWR nLWR MODE0 MODE1 MODE2 AVDD AVREF AN0 AN1 AN2 MODE3 External 16bit BUS MODE4 Flash boot mode with 16bit BUS MODE6 UART boot mode with 16bit BUS MODE5 Flash boot mode (MICOM mode) P15 P16 P17 P20 P21 P22 P23 P24 P25 P26 P27 P50 P51 P52 P53 P60 P61 P62 P67 nSTBY nRES nTRST P63 P64 P65 P66 Introduction MODE7 UART boot mode (MICOM mode) 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 73 75 76 77 78 79 80 Preliminary 23 Introduction Table 1.3 Pin assignment by mode (continued) PIN No. MODE2 External 8bit BUS AN3 AN4 VSS TIOCA5 TIOCB5 P75 nIRQ0 nCS3 nCS2 nCS1 nCS0 VSS TCLKA TCLKB TCLKC TCLKD A23 A22 A21 A20 MODE3 External 16bit BUS MODE4 Flash boot mode with 16bit BUS MODE6 Flash MCU(HMS39C7092) MODE5 Flash boot mode (MICOM mode) P81 P82 P83 P84 MODE7 UART boot mode (MICOM mode) UART boot mode with 16bit BUS TIOCA1 TIOCB1 TIOCA2 TIOCB2 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 24 Preliminary Flash MCU(HMS39C7092) 1.5 Memory Map 0 xFFFF FFFF 0x0900 2000 0 x0900 1FFF 0x0900 1000 0 x0900 0FFF 0x0900 0000 Introduction Reserved APB Register ASB Register Reserved Reserved ADC GPIO UART1 UART0 TIMER INTC WDT PMU 0 x0804 FFFF 0x0804 0000 0 x0803 FFFF 0x0803 0000 0 x0802 FFFF 0x0800 0000 0 x07FF FFFF On Chip BOOT ROM On Chip SRAM(4KB) FLASH nCS0 ~ nCS7 0 x0900 1FFF 0x0900 1800 0 x0900 17FF 0x0900 1700 0 x0900 16FF 0x0900 1600 0 x0900 15FF 0x0900 1500 0 x0900 14FF 0x0900 1400 0 x0900 13FF 0x0900 1300 0 x0900 12FF 0x0900 1200 0 x0900 11FF 0x0900 1100 0 x0900 10FF 0x0900 1000 0 x0900 0FFF Chip Select Area 0x0000 0000 Reserved 0x0900 0400 0 x0900 03FF 0x0900 0300 0 x0900 02FF 0x0900 0200 0 x0900 01FF 0x0900 0100 0 x0900 00FF 0x0900 0000 ARM7TEST FMI SMI MCUC Figure 1.3 HMS39C7092 Memory Map 0 x07FF FFFF 0 x07FF FFFF 0 x07FF FFFF 0 x07FF FFFF nCS7 0x0700 0000 0 x06FF FFFF nCS7 Reserved 0x0080 0000 0x0700 0000 0 x06FF FFFF Reserved 0x0080 0000 nCS6 0x0600 0000 0 x05FF FFFF nCS6 0x0600 0000 0 x05FF FFFF nCS5 0x0500 0000 0 x04FF FFFF nCS7 0 x007F FFFF 0x0070 0000 0 x006F FFFF 0x0060 0000 0 x005F FFFF 0x0050 0000 nCS5 0x0500 0000 0 x04FF FFFF nCS7 0 x007F FFFF 0x0070 0000 0 x006F FFFF 0x0060 0000 0 x005F FFFF 0x0050 0000 0 x004F FFFF 0x0040 0000 0 x003F FFFF 0x0030 0000 0 x002F FFFF 0x0020 0000 0 x001F FFFF 0x0010 0000 0 x000F FFFF 0x0000 1000 0 x0000 0FFF nCS4 0x0400 0000 0 x03FF FFFF nCS6 nCS5 nCS4 0x0400 0000 0 x03FF FFFF nCS6 nCS5 nCS3 0x0300 0000 nCS3 nCS4 0 x004F FFFF 0x0040 0000 0 x003F FFFF 0x0030 0000 0 x002F FFFF 0x0020 0000 0 x001F FFFF 0x0010 0000 0 x000F FFFF 0x0300 0000 nCS4 0 x02FF FFFF 0 x02FF FFFF nCS2 0x0200 0000 0 x01FF FFFF nCS3 nCS2 0x0200 0000 0 x01FF FFFF nCS3 nCS1 nCS2 0x0100 0000 0 x00FF FFFF nCS1 nCS2 0x0100 0000 0 x00FF FFFF nCS1 nCS1 nCS0 0x0000 1000 nCS0 0x0000 0000 nCS0 nCS0 0x0000 0000 0 x0000 0FFF On Chip SRAM 0x0000 0000 On Chip SRAM 0x0000 0000 Default. SM=0 in the PMU register. SM=1 in the PMU register. Remap mode (Remap = 1 ) SM=0 in the PMU register. Remap mode (Remap = 1 ) SM=1 in the PMU register. Figure 1.4 Memory Map of Mode 3 Preliminary 25 Introduction 0 x07FF FFFF 0 x07FF FFFF Flash MCU(HMS39C7092) 0 x07FF FFFF 0 x07FF FFFF 0x0700 0000 0 x06FF FFFF nCS7 nCS7 Reserved nCS6 0x0080 0000 0x0700 0000 0 x06FF FFFF 0x0600 0000 0 x05FF FFFF Reserved 0x0080 0000 nCS6 0x0600 0000 0 x05FF FFFF nCS5 0x0500 0000 0 x04FF FFFF nCS7 nCS6 nCS5 nCS4 0x007F FFFF 0x0070 0000 0x006F FFFF 0x0060 0000 0x005F FFFF 0x0050 0000 nCS5 0x0500 0000 0 x04FF FFFF nCS7 nCS6 nCS5 nCS4 0x007F FFFF 0x0070 0000 0x006F FFFF 0x0060 0000 0x005F FFFF 0x0050 0000 0x004F FFFF 0x0040 0000 0x003F FFFF 0x0030 0000 0x002F FFFF 0x0020 0000 0x001F FFFF 0x0010 0000 0x000F FFFF nCS4 0x0400 0000 0 x03FF FFFF nCS4 0x0400 0000 0 x03FF FFFF nCS3 0x0300 0000 0 x02FF FFFF nCS3 0x004F FFFF 0x0040 0000 0x003F FFFF 0x0030 0000 0x002F FFFF 0x0020 0000 0x001F FFFF 0x0010 0000 0x000F FFFF 0x0300 0000 0 x02FF FFFF nCS2 0x0200 0000 0 x01FF FFFF nCS3 nCS2 nCS1 nCS2 0x0200 0000 0 x01FF FFFF nCS3 nCS2 nCS1 nCS1 0x0100 0000 0 x00FF FFFF nCS1 0x0100 0000 0 x00FF FFFF nCS0 0x0003 0000 0 x0002 FFFF nCS0 0x0003 0000 0 x0002 FFFF nCS0 nCS0 FLASH (192KB) On Chip SRAM(4KB) 0x0003 0000 0 x0002 FFFF 0x0000 1000 0x0000 0FFF 0x0000 0000 0x0003 0000 0 x0002 FFFF FLASH (192KB) On Chip SRAM(4KB) 0x0000 1000 0x0000 0FFF 0x0000 0000 FLASH (192KB) 0x0000 0000 FLASH (192KB) 0x0000 0000 Default. SM=0 in the PMU register. SM=1 in the PMU register. R e m a p mode ( R e m a p = 1 ) SM=0 in the PMU register. R e m a p mode (R e m a p = 1 ) SM=1 in the PMU register. Figure 1.5 Memory Map of when Mode 4 and Mode 5 0 x07FF FFFF 0 x07FF FFFF 0x07FF FFFF 0x07FF FFFF nCS7 0x0700 0000 0 x06FF FFFF nCS7 Reserved nCS6 0x0080 0000 0x0700 0000 0x06FF FFFF 0x0600 0000 0x05FF FFFF 0x0080 0000 Reserved nCS6 0x0600 0000 0 x05FF FFFF nCS5 0x0500 0000 0 x04FF FFFF nCS7 nCS6 nCS5 nCS4 0 x007F FFFF 0x0070 0000 0 x006F FFFF 0x0060 0000 0 x005F FFFF 0x0050 0000 0 x004F FFFF 0x0040 0000 0 x003F FFFF 0x0030 0000 0 x002F FFFF 0x0020 0000 0 x001F FFFF 0x0010 0000 0 x000F FFFF nCS5 0x0500 0000 0x04FF FFFF nCS7 nCS6 nCS5 nCS4 0x007F FFFF 0x0070 0000 0x006F FFFF 0x0060 0000 0x005F FFFF 0x0050 0000 0x004F FFFF 0x0040 0000 0x003F FFFF 0x0030 0000 0x002F FFFF 0x0020 0000 0x001F FFFF 0x0010 0000 0x000F FFFF nCS4 0x0400 0000 0 x03FF FFFF nCS4 0x0400 0000 0x03FF FFFF nCS3 0x0300 0000 0 x02FF FFFF nCS3 0x0300 0000 0x02FF FFFF nCS2 0x0200 0000 0 x01FF FFFF nCS3 nCS2 nCS1 nCS2 0x0200 0000 0x01FF FFFF nCS3 nCS2 nCS1 nCS1 0x0100 0000 0 x00FF FFFF nCS1 0x0100 0000 0x00FF FFFF nCS0 0x0003 0000 0x0002 FFFF nCS0 0x0000 0100 0 x0000 00FF nCS0 nCS0 0x0003 0000 0x0002 FFFF 0x0000 0100 0 x0000 00FF On Chip Boot ROM (256Byte) 0x0000 0000 On Chip Boot ROM (256Byte) SM=1 and OnFLASH =0 in the PMU register. FLASH (192KB) 0x0000 1000 0x0000 0FFF 0x0000 0000 FLASH (192KB) 0x0000 1000 0x0000 0FFF 0x0000 0000 0x0000 0000 Default. SM=0 in the PMU register. SM=0 and On FLASH=1 in the PMU register. SM=1 and OnFLASH =1 in the PMU register. Figure 1.6 Memory Map of Mode 6 and Mode 7 26 Preliminary Flash MCU(HMS39C7092) ARM7TDMI Core Chapter 2 ARM7TDMI Core Preliminary 27 ARM7TDMI Core 2.1 General Description Flash MCU(HMS39C7092) The ARM7TDMI is a member of the ARM family of general-purpose 32bit microprocessors, which offers high performance for very low power consumption and price. This processor employs a unique architectural strategy known as THUMB, which makes it ideally suited to high volume applications with memory restrictions or applications where code density is an issue. The key idea behind THUMB is a super reduced instruction set. Essentially, the ARM7TDMI has two instruction sets, the standard 32bit ARM set and 16bit THUMB set. The THUMB set s 16bit instruction length allows it to approach twice the density ' of standard ARM code while retaining most of the ARM's performance advantage over a traditional 16bit processor by using 16bit registers. This is possible because THUMB code operates on the same 32bit register set as ARM code. See also ARM7TDMI Datasheet (ARM DDI 0029E) for detail. 2.2 Feature * 32bit RISC architecture * Low power consumption * ARM7TDMI core with; - On-chip ICEbreaker debug support - 32bit x 8 hardware multiplier - Thumb decompressor * Utilizes the ARM7TDMI embedded processor - High performance 32 bit RISC architecture - High density 16 bit instruction set (THUMB code) * Fully static operation : 0 ~ 80MHz * 3-stage pipeline architecture (Fetch, decode, and execution stage) * Enhanced ARM software toolkit THUMB code is able to provide up to 65% of the code size of ARM, and 160% of the performance of an equivalent ARM processor connected to a 16-bit memory system. 28 Preliminary Flash MCU(HMS39C7092) 2.3 Core Block Diagram ARM7TDMI Core ScanChain2 A [31:0] ALE ABE I n c r e m e n t e r b u s Scan Control Address Register P C b u s A L U b u s Address Incrementer Register Bank (31 x 32-bit registers) (6 status registers) 32 x 8 Multiplier Barrel Shifter 32-bit ALU Write Data Register nENOUT D B E nENIN Instruction Decoder & Control Logic DBGRQI BREAKPTI DBGACK ECLK nEXEC ISYNC BL [3:0] APE MCLK nWAIT nIRQ nFIQ nRESET ABORT RANGEOUT0 ICE Breaker RANGEOUT1 ESTERN1 EXTERN0 nRW MAS [1:0] nTRANS nMREQ nOPC A b u s B b u s SEQ LOCK nCPI CPA CPB nM [4:0] TBE TBIT HIGHZ A [0:31] Instruction Pipeline & Read Data Register & Thumb Instruction Decoder D [31:0] Core Scan Chain 1 Bus Splitter D [0:31] DIN [0:31] DOUT [0:31] Scan Chain 0 TAP Controller SCREG [3:0] IR [3:0] TASPM [3:0] TDO TDI nTRST TMS TCK Figure 2.1 ARM7TDMI Core Block Diagram Preliminary 29 ARM7TDMI Core 2.4 2.4.1 Flash MCU(HMS39C7092) Instruction Set ARM Instruction 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Cond Cond Cond Cond Cond Cond Cond Cond Cond Cond Cond Cond Cond Cond 0 0 I Opcode S 0 000 00A S 0 0 0 0 1 UA S 0 0 0 1 0 B0 0 Rn Rd RdHi Rn Rd Rn RdLo Rd Rs Rn Operand 1001 1001 Rm Rm Rm Rn Rm Data Processi ng / PSR Transfer Multiply Multiply Long Single Data Swap Branch and Exchange Halfword Data Transfer: register offset Halfword Data Transfer: immediate offset Single Data Transfer Undefined Block Data Transfer Branch 00001001 000100101111111111110001 0 0 0 P U0WL 0 0 0 P U1WL 0 1 I P U BW L 011 1 0 0 P U SW L 101L 1 1 0 P U NW L 1 1 1 0 CP Opc 1110 CP L Opc Rn CRn CRn Rn Register List Offset CRd CRd Rd CP# CP# CP# CP CP Offset 0 1 Rn Rn Rn Rd Rd Rd 0 0 0 0 1 S H1 Offset 1 S H 1 Offset Offset 1 Coprocessor Data Transfer Coprocessor Data Operation CRm CRm Coprocessor Register Transfer Cond 1111 Ignored by processor Software Interrupt 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Figure 2.2 ARM instruction set formats 30 Preliminary Flash MCU(HMS39C7092) Table 2.1 The ARM Instruction set Mnemonic Instruction ADC ADD AND B BIC BL BX CDP CMN CMP EOR LDC LDM LDR MCR MLA MOV MRC MRS MSR MUL MVN ORR RSB RSC SBC STC STM STR SUB SWI SWP TEQ TST Add with carry Add AND Branch Bit Clear Branch with Link Branch and Exchange Coprocessor Data Processing Compare Negative Compare Exclusive OR Load coprocessor from memory Load multiple registers Load register from memory Move CPU register to coprocessor register Multiply Accumulate Move register or constant Move from coprocessor register to CPU register Move PSR status/flags to register Move register to PSR status/flags Multiply Move negative register OR Reverse Subtract Reverse Subtract with Carry Subtract with Carry Store Multiple Store register to memory Subtract Software Interrupt Swap register with memory Test bitwise equality Test bits Rd := Rn + Op2 Rd := Rn AND Op2 R15 := address Rd := Rn AND NOT Op2 ARM7TDMI Core Action Rd := Rn + Op2 + Carry R14 := R15, R15 := address R15 := Rn, T bit := Rn[0] (Coprocessor-specific) CPSR flags := Rn + Op2 CPSR flags := Rn - Op2 Rd := (Rn AND NOT Op2) OR (op2 AND NOT Rn) Coprocessor load Stack manipulation (Pop) Rd := (address) cRn := rRn { Store coprocessor register to memory address := CRn Preliminary 31 ARM7TDMI Core ARM state General Registers and Program Counter System & User R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 (PC) FIQ R0 R1 R2 R3 R4 R5 R6 R7 R8_fiq R9_fiq R10_fiq R11_fiq R12_fiq R13_fiq R14_fiq R15 (PC) Supervisor R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_svc R14_svc R15 (PC) Flash MCU(HMS39C7092) Abort R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_abt R14_abt R15 (PC) IRQ R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_irq R14_irq R15 (PC) Undefined R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_und R14_und R15 (PC) ARM state Program Status Registers CPSR CPSR SPSR_fiq CPSR SPSR_svc CPSR SPSR_abt CPSR SPSR_irq CPSR SPSR_und = banked register Figure 2.3 Register Organization in ARM state 32 Preliminary Flash MCU(HMS39C7092) 2.4.2 THUMB Instruction 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 9 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 0 0 1 0 0 0 0 0 1 0 0 1 1 1 0 0 0 1 1 1 1 8 7 6 5 4 Rs Rs Offset8 Op Op Rd B S 0 1 Ro Ro H1 H2 Rs Rs/Hs Word8 Rb Rb Rb Rb Word8 Word8 0 R S SWord7 Rlist Rlist Soffset8 1 Value8 Offset11 Offset11 8 7 6 5 4 3 2 1 0 Rd Rd Rd Rd Rd Rd/Hd 3 2 1 Rd Rd 0 ARM7TDMI Core Offset5 I Op Rn/offset3 Rd 0 1 Move shifted register Add/subtract Move/compare/add/subtract immediate ALU operation Hi register operations/branch exchange PC-relative load Load/store with register Offset Load/store sign-extended byte/halfword Load/store with immediate Load/store halfword SP-relative load/store Load address Add offset to stack pointer Push/pop registers Multiple load/store Conditional branch Software Interrupt Unconditional branch Long branch with link Op 0 0 0 1 1 B 0 1 0 0 1 L H L L L Offset5 Offset5 Rd Rd 0 1 0 0 Rb Cond 10 1 11 1 12 1 13 1 14 1 15 1 16 1 17 1 18 1 19 1 0 SP 1 1 0 1 1 0 1 1 0 H 0 L L 1 1 15 14 13 12 11 10 9 Figure 2.4 THUMB instruction set formats Preliminary 33 ARM7TDMI Core Table 2.2 THUMB instruction set opcodes Mnemonic Instruction Lo reg. oper. ADC ADD AND ASR B B xx BIC BL BX CMN CMP EOR LDMIA LDR LDRB LDRH LSL LDSB LDSH LSR MOV MUL MVN NEG ORR POP PUSH ROR SBC STMIA STR STRB STRH SWI SUB TST Add with Carry Add AND Arithmetic Shift Right Unconditional branch Conditional branch Bit Clear Branch and Link Branch and Exchange Compare Negative Compare EOR Load multiple Load word Load byte Load halfword Logical Shift Left Load sign-extended byte Load sign-extended Halfword Logical Shift Right Move register Multiply Move Negative register Negate OR Pop registers Push registers Rotate Right Subtract with Carry Store Multiple Store word Store byte Store halfword Software Interrupt Subtract Test bits V V V V V V V V V V V V V V V V V V V V V V V V V V V Flash MCU(HMS39C7092) Hi reg. oper V Condition code set V V V V V V V V V V V V V V V V V V V V V V V V V V V V V 34 Preliminary Flash MCU(HMS39C7092) THUMB state General Registers and Program Counter System & User R0 R1 R2 R3 R4 R5 R6 R7 SP LR PC FIQ R0 R1 R2 R3 R4 R5 R6 R7 SP_fiq LR_fiq PC Supervisor R0 R1 R2 R3 R4 R5 R6 R7 SP_svc LR_svc PC Abort R0 R1 R2 R3 R4 R5 R6 R7 SP_abt LR_abt PC ARM7TDMI Core IRQ R0 R1 R2 R3 R4 R5 R6 R7 SP_irq LR_irq PC Undefined R0 R1 R2 R3 R4 R5 R6 R7 SP_und LR_und PC THUMB state Program Status Registers CPSR CPSR SPSR_fiq CPSR SPSR_svc CPSR SPSR_abt CPSR SPSR_irq CPSR SPSR_und = banked register Figure 2.5 Register Organization in THUMB state THUMB state R0 R1 R2 R3 R4 R5 R6 R7 Stack Pointer (SP) Link Register (LR) Program Counter (PC) CPSR SPSR ARM state R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 Stack Pointer (R13) Link Register (R14) Program Counter (R15) CPSR SPSR Figure 2.6 Mapping of THUMB state registers onto ARM state registers. Lo registers Hi registers Preliminary 35 ARM7TDMI Core Table 2.3 Condition code summary Flash MCU(HMS39C7092) Suffix EQ NE CS CC MI PL VS VC HI LS GE LT GT LE AL Flags Z Z C C N N V V C C N N Z Z (Ignored) set equal clear not equal set unsigned higher or same clear unsigned lower set negative clear positive or zero set overflow clear no overflow set and Z clear unsigned higher clear or Z set unsigned lower or same equals V greater or equal not equal to V less than clear AND (N equals V) greater than set OR (N not equal to V) less than or equal always Code 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 Meaning 2.4.3 The Program Status Registers The ARM7TDMI contains Current Program Status Register (CPSR), plus five Saved Program Status Register (SPSRs) for use by exception handlers. These registers hold information about the most recently performed ALU operation control the enabling and disabling of interrupts set the processor operating mode The arrangement of bits is shown in Fig. 2.7 Program status register format. Condition code flags 31 N (reserved) 26 . Control bits 8 ... ... 30 Z 29 C 28 V 27 . 25 . 24 . 23 .... 7 I 6 F 5 T 4 M4 3 M3 2 M2 1 M1 0 M0 Overflow Carry / Borrow / Extend Zero Negative / Less Than Figure 2.7 Program status register format Mode bits State bit FIQ disable IRQ disable 36 Preliminary Flash MCU(HMS39C7092) 2.4.3.1 The condition code flags ARM7TDMI Core The N,Z,C and V bits are the condition code flags. These may be changed as a result of arithmetic and logical operations, and may be tested to determine whether an instruction should be executed. In ARM state, all instructions may be executed conditionally : see table 2.3 in chapter 2.4.2. In THUMB state, only the Branch instruction is capable of conditional execution 2.4.3.2 The control bits The bottom 8 bits of a PSR(incorporating I,F,T and M[4:0]) are known collectively as the control bits. These will change when an exception arises. If the processor is operating in a privileged mode, they can also be manipulated by s oftware. The T bit This reflects the operating states. When this bit is set, the processor is executing in THUMB state, otherwise it is executing in ARM state. Note that the software must never change the state of the TBIT in the CPSR. If this happens, the processor will enter an unpredictable state. Interrupt disable bits The I and F bits are the interrupt disable bits. When set, these disable the IRQ and FIQ interrupts respectively. The M4, M3, M2, M1 and M0 bits (M[4:0]) are the mode bits. These determine the processor's operating mode, as shown in following table 2.4. Not all combinations of the mode bits define a valid processor mode. Only those explicitly described shall be used. The user should be aware that if any illegal value is programmed into the mode bits, M{4:0}, then the processor will enter an unrecoverable state. If this occurs, reset should be applied. The remaining bits in the PSRs are reserved. When changing a PSR's flag or control bits, you must ensure these unused bits are not altered. Also, your program should not rely on them containing specific values, since in future processors they may read as one or zero. The mode bits Reserved bits Preliminary 37 ARM7TDMI Core Table 2.4 PSR mode bit values Flash MCU(HMS39C7092) M[4:0] 10000 Mode User 10001 FIQ 10010 IRQ 10011 Supervisor 10111 Abort 11011 Undefined 11111 System Visible THUMB state registers R7..R0, LR, SP, PC, CPSR R7..R0, LR_fiq, SP_fiq, PC, CPSR, SPSR_fiq R7..R0, LR_irq, SP_irq, PC, CPSR, SPSR_irq R7..R0, LR_svc, SP_svc, PC, CPSR, SPSR_svc R7..R0, LR_abt, SP_abt, PC, CPSR, SPSR_abt R7..R0, LR_und, SP_und, PC, CPSR, SPSR_und R7..R0, LR, SP, PC, CPSR Visible ARM registers R14..R0, PC, CPSR state R7..R0, R14_fiq...R8_fiq, PC, CPSR, SPSR_fiq R12..R0, R14_irq, R13_irq, PC, CPSR, SPSR_irq R12..R0, R14_svc, R13_svc, PC, CPSR, SPSR_svc R12..R0, R14_abt, R13_abt, PC, CPSR, SPSR_abt R12..R0, R14_und, R13_und, PC, CPSR R14..R0, PC, CPSR 38 Preliminary Flash MCU(HMS39C7092) 2.4.4 ARM pseudo-instructions ARM7TDMI Core ADR The ADR pseudo-instruction loads a program-relative or register-relative address into a register. Syntax The syntax of ADR is: ADR{ condition} register, expression where: register is the register to load. expression is a program-relative or register-relative expression that evaluates to: * a non word-aligned address wihin 255 bytes t * a word-aligned address within 1020 bytes. The address can be either before or after the address of the instruction or the base register. Usage ADR always assembles to one instruction. The assembler attempts to produce a single ADD or SUB instruction to load the address. If the address cannot be constructed in a single instruction, an error is generated and the assembly fails. Use the ADRL pseudo-instruction to assemble a wider range of effective addresses. If expression is program-relative, it must evaluate to an address in the same code area as the ADR pseudo-instruction. Otherwise the address may be out of range after linking. Example start MOV r0,#10 ADR r4,start ; => SUB r4,pc,#0xc Preliminary 39 ARM7TDMI Core ADRL Flash MCU(HMS39C7092) The ADRL pseudo-instruction loads a program-relative or register-relative address into a register. It is similar to the ADR pseudo-instruction. ADRL can load a wider range of addresses than ADR because it generates two data processing instructions. Syntax The syntax of ADRL is: ADRL{ condition} register, expression where: register is the register to load. expression is a register-relative or program-relative expression that evaluates to: * a non word-aligned address within 64KB * a word-aligned address within 256KB. The address can be either before or after the address of the instruction or the base register. Usage ADRL always assembles to two instructions. Even if the address can be reached in a single instruction, a second, redundant instruction is produced. If the assembler cannot construct the address in two instructions, it generates an error message and the assembly fails. See LDR ARM pseudo-instruction for information on loading a wider range of addresses. See also Chapter 5 Basic Assembly Language Programming in the ARM Software Development Toolkit User Guide. If expression is program-relative, it must evaluate to an address in the same code area as the ADRL pseudo-instruction. Otherwise the address may be out of range after linking. Note ADRL is not available when assembling Thumb instructions. Use it only in ARM code. Example start MOV r0,#10 ADRL r4,start + 60000 ; => ADD r4,pc,#0xe800 ; ADD r4,r4,#0x254 40 Preliminary Flash MCU(HMS39C7092) LDR The LDR pseudo-instruction loads a register with either: * a 32-bit constant value * an address. Note ARM7TDMI Core This section describes the LDR pseudo-instruction only. Refer to the ARM Architectural Reference Manual for information on the LDR instruction. Syntax The syntax of LDR is: LDR{ condition} register, =[ expression | label -expression] where: condition is an optional condition code. register is the register to be loaded. expression evaluates to a numeric constant: * If the value of expression is within range of a MOV or MVN instruction, the assembler generates the appropriate instruction. * If the value of expression is not within range of a MOV or MVN instruction, the assembler places the constant in a literal pool and generates a program-relative LDR instruction that reads the constant from the literal pool. The offset from the pc to the constant must be less than 4KB. You are responsible for ensuring that there is a literal pool within range. See LTORG directive for more information. label-expression is a program-relative or external expression. The assembler places the value of label-expression in a literal pool and generates a program-relative LDR instruction that loads the value from the literal pool. The offset from the pc to the value in the literal pool must be less than 4KB. You are responsible for ensuring that there is a literal pool within range. See LTORG directive for more information. If label-expression is an external expression, or is not contained in the current area, the assembler places a linker relocation directive in the object file. The linker ensures that the correct address is generated at link time. Usage The LDR pseudo-instruction is used for two main purposes: * to generate literal constants when an immediate value cannot be moved into a register because it is out of range of the MOV and MVN instructions. * to load a program-relative or external address into a register. The address remains valid regardless of where the linker places the AOF area containing the LDR. Refer to Chapter 5 Basic Assembly Language Programming in the ARM Software Development Toolkit User Guide for a more detailed explanation of how to use LDR, and for more information on MOV and MVN. Example LDR r1,=0xfff LDR r2,=place ; loads 0xfff into r1 ; ; loads the address of ; place into r2 Preliminary 41 ARM7TDMI Core NOP Flash MCU(HMS39C7092) NOP generates the preferred ARM no-operation code. This is: MOV r0,r0 Syntax The syntax of NOP is: NOP Usage NOP cannot be used conditionally. Not executing a no-operation is the same as executing it, so conditional execution is not required. Condition codes are unaltered by NOP. 42 Preliminary Flash MCU(HMS39C7092) 2.4.5 THUMB pseudo-instructions ARM7TDMI Core ADR The thumb ADR pseudo-instruction loads a program-relative or register-relative address into a register. Syntax The syntax of ADR is: ADR register, expression where: register is the register to load. Expression is a register-relative or program-relative expression that evaluates to a word-aligned address within the range +4 to +1020 bytes. Expression must be defined locally, it cannot be imported. Refer to ^ or MAP directive for more information on register-relative expressions. Usage In Thumb state, ADR can generate word-aligned addresses only. Use the ALIGN directive to ensure that expression is aligned. If expression is program-relative, it must evaluate to an address in the same code area as the ADR pseudo-instruction. There is no guarantee that the address will be within range after linking if it resides in another AOF area. Example ADR r4, txampl ; code ALIGN DCW 0,0,0,0 ; => ADD r4,pc,#nn txampl Preliminary 43 ARM7TDMI Core LDR Flash MCU(HMS39C7092) The thumb LDR pseudo-instruction loads a low register with either: * a 32-bit constant value * an address. Note This section describes the LDR pseudo-instruction only. Refer to the ARM Architectural Reference Manual for information on the LDR instruction. Syntax The syntax of LDR is: LDR register, =[ expression | label -expression] where: register is the register to be loaded. LDR can access the low registers (r0-r7) only. expression evaluates to a numeric constant: * If the value of expression is within range of a MOV instruction, the assembler generates the instruction. * If the value of expression is not within range of a MOV instruction, the assembler places the constant in a literal pool and generates a program-relative LDR instruction that reads the constant from the literal pool. The offset from the pc to the constant must be positive and less than 1KB. You are responsible for ensuring that there is a literal pool within range. See LTORG directive for more information. label-expression is a program-relative or external expression. The assembler places the value of label-expression in a literal pool and generates a program-relative LDR instruction that loads the value from the literal pool. The offset from the pc to the value in the literal pool must be positive and less than 1KB. You are responsible for ensuring that there is a literal pool within range. See LTORG directive for more information. If label-expression is an external expression, or is not contained in the current area, the assembler places a linker relocation directive in the object file. The linker ensures that the correct address is generated at link time. Usage The LDR pseudo-instruction is used for two main purposes: * to generate literal constants when an immediate value cannot be moved into a register because it is out of range of the MOV instruction. * to load a program-relative or external address into a register. The address remains valid regardless of where the linker places the AOF area containing the LDR. Refer to Chapter 5 Basic Assembly Language Programming in the ARM Software Development Toolkit User Guide for a more detailed explanation of howto use LDR, and for more information on MOV. Example LDR r1, =0xfff LDR r2, = labelname ; loads 0xfff into r1 ; ; loads the address of ; labelname into r2 44 Preliminary Flash MCU(HMS39C7092) MOV ARM7TDMI Core The Thumb MOV pseudo-instruction moves the value of a low register to another low register (r0-r7). The Thumb MOV instruction cannot move values from one low register to another. Note The ADD immediate instruction generated by the assembler has the side-effect of updating the condition codes. Syntax The syntax of MOV is: MOV Rd, Rs where: Rd is the destination register. Rs is the source register. Usage The MOV pseudo-instruction uses an ADD immediate instruction with a zero immediate value. Refer to the ARM Architectural Reference Manual for more information on the Thumb MOV instruction. Example MOV Rd, Rs ; generates the opcode for ADD Rd, Rs, #0 Preliminary 45 ARM7TDMI Core NOP Flash MCU(HMS39C7092) NOP generates the preferred Thumb no-operation instruction. This is: MOV r8,r8 Syntax The syntax for NOP is: NOP Usage Condition codes are unaltered by NOP 46 Preliminary Flash MCU(HMS39C7092) BUS controller Chapter 3 BUS Controller Preliminary 47 BUS controller 3.1 Overview Flash MCU(HMS39C7092) The HMS39C7092 has an on-chip bus controller that manages the external address space divided into eight areas, which can attaches SRAM, ROM, Flash-memory or off-chip peripheral devices. The bus specifications, such as bus width and number of access states, can be set independently for each area, enabling multiple memories to be connected easily. 3.1.1 Features The features of the bus controller are listed below. * 8-bit access or 16-bit access can be selected for each area (In THUMB mode, only 16-bit accessing of external code memory is allowed) * Active low chip select signals (nCS0 to nCS7) can be output for area 0 to 7 * Bus specifications can be set independently for each area * Support Little-Endian Memory Format * Variable wait states (up to 16 waits) * Bus transfers can be extended using the nWAIT signal. The nWAIT signal is active LOW * Each area is 16MB(when SM='0' in PMU), or 1MB(when SM='1' in PMU) in Size and can be programmed individually. nCS[7:0] SM MD[2:0] Address Decoder Main State Machine Internal Address BUS nAS nHWR nLWR nRD External BUS Control Signals BUS control Register Pack Internal Data BUS (BCRn) nWAIT Wait State Controller Wait Configuration Reg. nBREQ nBACK Bus Arbiter Internal signals Bus reset / Clock signal Access Control signal BUS size signals BUS slave signals Figure 3.1 Block Diagram of the Bus Controller 48 Preliminary Flash MCU(HMS39C7092) 3.1.2 Pin Configuration BUS controller Table 3.1 summarizes the input/output pins of the bus controller. Table 3.1 Bus Controller Pins Name I/O Function nCSn O Strobe signals selecting areas 0 to 7 nAS O Strobe signal indicating valid address output on the address bus nRD O Strobe signal indicating reading from the external address space nHWR O Strobe signal indicating writing to the external address space, with valid data on the upper data bus (D15 to D8) nLWR O Strobe signal indicating writing to the external address space, with valid data on the lower data bus (D7 to D0) nWAIT I Wait request signal nBREQ I Request signal for releasing the bus to an external device nBACK O Acknowledge signal indicating release of the bus to an external device Preliminary 49 BUS controller 3.2 Bus Controller Registers Flash MCU(HMS39C7092) The base address for the BUS Controller's registers is 0x0900_0100. Each configuration registers (BCR0~7) are assigned to chip selected area, CS0~CS7. Table 3.2 BUS Controller Register Map I/O Reg. Dir. Offset Description BCR0 BCR1 BCR2 BCR3 BCR4 BCR5 BCR6 BCR7 Notes : 0x0100 0x0104 0x0108 0x010C 0x0110 0x0114 0x0118 0x011C R/W R/W R/W R/W R/W R/W R/W R/W CS0 Bus Configuration Register CS1 Bus Configuration Register CS2 Bus Configuration Register CS3 Bus Configuration Register CS4 Bus Configuration Register CS5 Bus Configuration Register CS6 Bus Configuration Register CS7 Bus Configuration Register Initial Value 0x00F* 0x0 0x0 0x0 0x0 0x0 0x0 0x0 1) In mode 2, the initial value of BCR0 is 0x010F. 2) In mode 3, the initial value of BCR0 is 0x000F. 3) The initial value of the other control registers are 0x0000. 50 Preliminary Flash MCU(HMS39C7092) 3.2.1 Configuration Registers BUS controller The configuration register (BCR0~7) is a 16-bit read-write register. BCR0~7 Bus Configuration Register (0x0900_0100 to 0x0900_011C R/W) B15 - b9 BCRn Reset Reserved 0000000 b8 MemWidth 1 b7 Reserved 0 0 B6 B5 Reserved 0 0 1 b4 b3 b2 b1 b0 Normal Wait 1 1 1 Initial value : 0x010F (BCR0 at Mode2) 0x000F (BCR0 at Mode3) 0x0000 (BCR1~7) MemWidth Select the size of the external bus width. When this bit is 0, means that the MCU interface with 8bit external bus. When 1, the external bus of the MCU is 16 bit width bus. NormWait Select the values of the normal access wait state 0000 : 1 wait state 0001 : 2 wait state 0010 : 3 wait state 0011 : 4 wait state 0100 : 5 wait state 0101 : 6 wait state 0110 : 7 wait state 0111 : 8 wait state 1000 : 9 wait state 1001 : 10 wait state 1010 : 11 wait state 1011 : 12 wait state 1100 : 13 wait state 1101 : 14 wait state 1110 : 15 wait state 1111 : 16 wait state Preliminary 51 BUS controller 3.3 3.3.1 Flash MCU(HMS39C7092) Operation Area Division The external address space is divided into area 0 to 7. Each area has a size of 16Mbyte modes, or 1-Mbyte modes. Figure 3.2 shows a general view of the memory map. nCS7 0x07FF FFFF 0x0700 0000 0x06FF FFFF 0x0600 0000 0x05FF FFFF Reserved 0x07FF FFFF nCS6 nCS5 nCS7 nCS4 0x0500 0000 0x04FF FFFF 0x0400 0000 0x03FF FFFF 0x0300 0000 0x02FF FFFF 0x0200 0000 0x01FF FFFF 0x0100 0000 0x00FF FFFF 0x0000 0000 a) 16- Mbyte modes (Default) SM=0 in the PMU register. Figure 3.2 nCS6 nCS5 nCS4 nCS3 nCS2 nCS1 nCS1 0x0080 0000 0x007F FFFF 0x0070 0000 0x006F FFFF 0x0060 0000 0x005F FFFF 0x0050 0000 0x004F FFFF 0x0040 0000 0x003F FFFF 0x0030 0000 0x002F FFFF 0x0020 0000 0x001F FFFF 0x0010 0000 0x000F FFFF 0x0000 0000 nCS3 nCS2 nCS1 nCS0 b) 1-Mbyte mode SM=1 in the PMU register. Access Area Map for Each Operating Mode Chip select signals ( CS0 to nCS 7) can be output for area 0 to 7. The bus n specifications for each area are selected in BCR0 to BCR7. 52 Preliminary Flash MCU(HMS39C7092) 3.3.2 Area Division BUS controller The external space bus specifications consist of two elements: (1) bus width, (2) number of wait states. The bus width and number of access states for on-chip memory and registers are fixed, and are not affected by the bus controller. Bus Width: A bus width of 8 or 16 bits can be selected with MemWidth bit-field in BCR0 to 7. An area for which an 8-bit bus is selected functions as an 8-bit access space, and an area for which a 16-bit bus is selected functions as a 16-bit access space. If all areas are designed for 8-bit access, 8-bit bus mode is set; if any area is designed for 16-bit access, 16-bit bus mode is set. Number of Wait States: One to 16 wait states can be selected with NormalWait bitfield in BCR0 to 7. When using nWAIT signal, then wait state is the minimum over two-states. 3.3.3 Chip Select Signals For each of areas 0 to 7, the HMS39C7092 can output a chip select signal (nCS0 to nCS7) that goes low when the corresponding area is selected in expanded mode. From Figure 3.3 to Figure 3.15 shows the output timing of nCS0 ~ 7 signal. Output of nCS 0 to nCS 7 : Output of nCS0 to nCS 7 is enabled or disabled in the data direction register of the corresponding port. Preliminary 53 BUS controller 3.4 3.4.1 Flash MCU(HMS39C7092) Basic Bus Interface Overview The HMS39C7092 has only a basic interface that allows direct connection of ROM, SRAM, off-chip peripheral devices and so on. 3.4.2 Byte Lane Write Control Data size for the CPU and other internal masters are byte(8-bit), half-word(16-bit), word(32-bit). The bus controller has a data alignment function, and when accessing external space, controls whether the upper data bus (D15 to D8) or lower data bus (D7 to D0) is used according to the bus specifications for the area being accessed (8-bit access area or 16-bit access area) and the data size. 8-Bit Access Areas: Figure 3.3 shows data alignment control for 8-bit access space. With 8-bit access space, the lower data bus (D7 to D0) is always used for accesses. The amount of data that can be accessed at one time is one byte: a half-word access is performed as two byte accesses, and a word access, as four byte accesses. Byte size Lower Byte 1st bus cycle Half-word size 2nd bus cycle Lower Byte Lower Byte 1st bus cycle 2nd bus cycle Word size 3rd bus cycle 4th bus cycle Lower Byte Lower Byte Lower Byte Lower Byte Figure 3.3 Access Size and Data Alignment Control (8-Bit Access Area) 54 Preliminary Flash MCU(HMS39C7092) BUS controller 16-Bit Access Areas: Figure 3.4 shows data alignment control for 16-bit access areas. With 16-bit access areas, the lower data bus (D7 to D0) and higher data bus (D15 to D8) are used for accesses. The amount of data that can be accessed at one time is one byte or one half-word, and a word access is executed as two half-word accesses. Byte size Even Address Odd Address Upper Byte Lower Byte Half-word size Upper Byte Lower Byte 1st bus cycle Word size 2nd bus cycle Upper Byte Lower Byte Upper Byte Lower Byte Figure 3.4 Access Size and Data Alignment Control (16-Bit Access Area) nHWR, nLWR signals are generated according to the memory transfer width, external memory width, A0, and the access sequencing. The following table shows the basic coding example assuming 16-bit external memory: Table 3.3 Byte Lane condition by XA[0] CPU access Size Word (32bit) Half-word (16-bit) Byte (8bit) Byte (8bit) A0 X X 0 1 nHWR Low Low High Low nLWR Low Low Low High Number of Access 2 1 1 1 Preliminary 55 BUS controller 3.4.3 Basic Bus Control Signal Timing Flash MCU(HMS39C7092) 16-Bit 1-Wait-Access Areas: Figure 3.5 shows the write timing of bus control signals for a 16-Bit 1-wait-access area (in case of 32-bit word access). Figure 3.6 shows the read timing of bus control signals for a 16-Bit 1-wait-access area (In case of 32-bit word access). In this case the NormWait value in BCR of this area is `0'. Note: Sequential read access keeps nRD signal to LOW state. XIN nCSn nAS Address Data nHWR nLWR `1' nRD n Valid n+2 Valid Figure 3.5 Bus Control Signal Write Timing for 16-Bit, 1-Wait (Word Access) XIN nCSn nAS Address Data nHWR nLWR nRD `1' `1' n Valid n+2 Valid Figure 3.6 Bus Control Signal Read Timing for 16-Bit, 1-Wait (Word Access) 56 Preliminary Flash MCU(HMS39C7092) BUS controller Figure 3.7 shows the write timing of bus control signals for a 16-Bit 1-wait-access area (In case of half-word access). Figure 3.8 shows the read timing of bus control signals for a 16-Bit 1-wait-access area (In case of half-word access). XIN nCSn nAS Address Data nHWR nLWR `1' nRD n Valid n+2 Valid Figure 3.7 Bus Control Signal Write Timing for 16-Bit, 1-Wait (Half-word Access) XIN nCSn nAS Address Data nHWR nLWR nRD `1' `1' n Valid n+2 Valid Figure 3.8 Bus Control Signal Read Timing for 16-Bit, 1-Wait (Half-word Access) Preliminary 57 BUS controller Flash MCU(HMS39C7092) Figure 3.9 shows the write timing of bus control signals for a 16-Bit 1-wait-access area (In case of byte access). Figure 3.10 shows the read timing of bus control signals for a 16-Bit 1-wait-access area (In case of byte access). XIN nCSn nAS Address Data `1' nHWR nLWR `1' nRD n Valid Figure 3.9 Bus Control Signal Write Timing for 16-Bit, 1-Wait (Byte Access) XIN nCSn nAS Address Data nHWR nLWR nRD n Valid Figure 3.10 Bus Control Signal Read Timing for 16-Bit, 1-Wait (Byte Access) 58 Preliminary Flash MCU(HMS39C7092) BUS controller Figure 3.11 shows the write timing of bus control signals for a 16-Bit 2-wait-access area (In case of word access). Figure 3.12 shows the read timing of bus control signals for a 16-Bit 2-wait-access area (In case of word access). XIN nCSn nAS Address Data nHWR nLWR `1' nRD n Valid n+2 Valid Figure 3.11 Bus Control Signal Write Timing for 16-Bit, 2-Wait (Word Access) XIN nCSn nAS Address Data nHWR nLWR nRD `1' `1' n Valid n+2 Valid Figure 3.12 Bus Control Signal Read Timing for 16-Bit, 2-Wait (Word Access) Preliminary 59 BUS controller Flash MCU(HMS39C7092) Figure 3.13 shows the write timing of bus control signals for a 16-Bit 2-wait-access area (In case of half-word access). Figure 3.14 shows the read timing of bus control signals for a 16-Bit 2-wait-access area (In case of half-word access). XIN nCSn nAS Address Data nHWR nLWR `1' nRD n Valid Figure 3.13 Bus Control Signal Write Timing for 16-Bit, 2-Wait (Half-Word Access) XIN nCSn nAS Address Data nHWR nLWR nRD n Valid Figure 3.14 Bus Control Signal Read Timing for 16-Bit, 2-Wait (Half-Word Access) 60 Preliminary Flash MCU(HMS39C7092) BUS controller Figure 3.15 shows the write timing of bus control signals for a 16-Bit 2-wait-access area (In case of byte access). Figure 3.16 shows the read timing of bus control signals for a 16-Bit 2-wait-access area (In case of byte access). XIN nCSn nAS Address Data `1' nHWR nLWR `1' nRD n Valid Figure 3.15 Bus Control Signal Write Timing for 16-Bit, 2-Wait (Byte Access) XIN nCSn nAS Address Data nHWR nLWR nRD n Valid Figure 3.16 Bus Control Signal Read Timing for 16-Bit, 2-Wait (Byte Access) Preliminary 61 BUS controller 3.4.4 Wait Control Flash MCU(HMS39C7092) When accessing external space, the HMS39C7092 can extend the bus cycle by inserting wait states (Tw). There are two ways of inserting wait states: (1) program wait insertion and (2) pin wait insertion using the nWAIT pin. Program Wait Insertion: From 1 to 16 wait states can be inserted automatically between the T2 state and T3 state on an individual basis in each access space, according to the settings of NormWait bit fields in BCR0~7. Pin Wait Insertion: When external space is accessed in this state, a program wait is first inserted. If the nWAIT pin is low at the falling edge of XIN in the last T2 or Tw state, another Tw state is inserted. If the nWAIT pin is held low, Tw states are inserted until it goes high. Figure 3.17 shows an example of the timing for insertion of one program wait state in 3-wait-state space. T1 XIN nWAIT nCSn nAS Address Data nHWR nLWR nRD `1' `1' n Valid T2 Tw Tw Tw T3 Figure 3.17 Example of Wait State Insertion Timing. 62 Preliminary Flash MCU(HMS39C7092) 3.4.5 Bus Arbiter BUS controller The bus controller has a built-in bus arbiter that arbitrates between different bus masters. The bus master can be either the CPU or an external bus master. When a bus master has the bus right it can carry out read and write operations. Each bus master uses a bus request signal to request the bus right. At fixed times the bus arbiter determines priority and uses a bus acknowledge signal to grant the bus to a bus master, which can operate using the bus. The bus arbiter checks whether the bus request signal from a bus master is active or inactive, and returns an acknowledge signal to the bus master. When two or more bus masters request the bus, the highest-priority bus master receives an acknowledge signal can continue to use the bus until the acknowledge signal is deactivated. The bus master priority order is: (High) External bus master > ARM CPU (Low) The bus arbiter samples the bus request signals and determines priority at all times, but it does not always grant the bus immediately, even when it receives a bus request a bus master with higher priority than the current bus master. Each bus master has certain times at which it can release the bus to a higher-priority bus master. ARM CPU: The ARM CPU is the lowest-priority bus master. If an external bus master requests the bus while the CPU has the right, the bus arbiter transfers the bus right to the bus master that requested it. The bus right is transferred at the following times: l The bus right is transferred at the boundary of a bus cycle. If word data is accessed by two consecutive byte accesses, however, the bus right is not transferred between the two byte accesses. l If another bus master requests the bus while the CPU is performing internal operations, such as executing a multiply or divide instruction, the bus right is transferred immediately. The CPU continues its internal operations. l If another bus master requests the bus while the CPU is in power down mode, the bus right is transferred immediately. External Bus Master: The HMS39C7092 can be always released to an external bus master. The external bus master has highest priority, and requests the bus right from the bus arbiter driving the nBREQ signal low. Once the external bus master acquires the bus, it keeps the bus until the nBREQ signal goes to high. While the bus is released to an external bus master, the HMS39C7092 chip holds the address bus, data bus, bus control signals (nAS, nRD, nHWR, and nLWR), and chip select signals (nCS0 to 7), and holds the nBACK pin in the low output state. The bus arbiter samples the nBREQ pin at the rise of the system clock (XIN). If nBREQ is low, the bus is released to the external bus master at the appropriate opportunity. The nBREQ signal should be held low until the nBACK goes low. When the nBREQ pin is high in two consecutive samples, the nBACK pin is driven high to end the bus -release cycle. Preliminary 63 BUS controller Flash MCU(HMS39C7092) Figure 3.18 shows the timing when the bus right is requested by an external bus master during a read cycle in a 1-wait-state access area. There is a minimum interval of three states from when the nBREQ signal goes low until the bus is released. CPU Cycle T0 XIN nBREQ nBACK nCSn nAS Address Data nHWR nLWR nRD `1' `1' n Valid T1 T2 Tw External Bus Cycle Tw T3 Figure 3.18 Example of External Bus Master Operation 64 Preliminary Flash MCU(HMS39C7092) MCU controller Chapter 4 MCU Controller Preliminary 65 MCU controller 4.1 General Description Flash MCU(HMS39C7092) The MCU Controller (MCUC) is composed of 11 multi-function pin multiplex control signal registers and device code register. 4.2 Pin Function Description Table 4.1 shows Pin function description. Table 4.1 Pin Function Descriptions NAME Port A Port No. Multiplexed functions NAME Port No. Multiplexed functions D0 D1 D2 D3 D4 D5 D6 D7 A16 A17 A18 A19 nWAIT nBREQ nBACK nAS nRD nHWR nLWR CLKO AN0 AN1 AN2 AN3 AN4 P75 TIOCA5, nIRQ6 TIOCB5, nIRQ7 nIRQ0 nCS3, nIRQ1 nCS2, nIRQ2 nCS1, nIRQ3 nCS0 TxD0 RxD0 TxD1 RxD1 XFVPPD* nTRST PA0 TCLKA P40 Port 4 PA1 TCLKB P41 PA2 TCLKC, TIOCA0 P42 PA3 TCLKD, TIOCB0 P43 PA4 A23, TIOCA1 P44 PA5 A22, TIOCB1 P45 PA6 A21, TIOCA2 P46 PA7 A20, TIOCB2 P47 PB0 nCS7, TIOCA3 P50 Port B Port 5 PB1 nCS6, TIOCB3 P51 PB2 nCS5, TUICA4 P52 PB3 nCS4, TIOCB4 P53 PB4 TMS P60 Port 6 PB5 TDO P61 PB6 TDI P62 PB7 TCK P63 P10 A0 P64 Port 1 P11 A1 P65 P12 A2 P66 P13 A3 P67 P14 A4 P70 Port 7 P15 A5 P71 P16 A6 P72 P17 A7 P73 P20 A8 P74 Port 2 P21 A9 P75 P22 A10 P76 P23 A11 P77 P24 A12 P80 Port 8 P25 A13 P81 P26 A14 P82 P27 A15 P83 P30 D8 P84 Port 3 P31 D9 P90 Port 9 P32 D10 P91 P33 D11 P92 P34 D12 P93 P35 D13 XP96* P36 D14 P97 P37 D15 *XP96/XFVPPD pin is package bonding options Note: Each port functions are changed by Mode-setting or user definition. Default functions are showed in 4.3.2 PINMUX Register 66 Preliminary Flash MCU(HMS39C7092) 4.3 4.3.1 MCU controller Register Description Register Memory Map Table 4.2 is the memory map of the MCU Controller. The base address of M CU control Register is 0x0900_0000. Table 4.3 shows the initial value in each mode. The initial values are different by operation mode. Table 4.2 Memory map of the MCU Controller I/O Dir. Description Reg. OFFSET PAMR 0x0000 R/W Pin MUX Control Register for Port A PBMR 0x0004 R/W Pin MUX Control Register for Port B P1MR 0x0008 R/W Pin MUX Control Register for Port 1 P2MR 0x000C R/W Pin MUX Control Register for Port 2 P3MR 0x0010 R/W Pin MUX Control Register for Port 3 P4MR 0x0014 R/W Pin MUX Control Register for Port 4 P5MR 0x0018 R/W Pin MUX Control Register for Port 5 P6MR 0x001C R/W Pin MUX Control Register for Port 6 P7MR 0x0020 R/W Pin MUX Control Register for Port 7 P8MR 0x0024 R/W Pin MUX Control Register for Port 8 P9MR 0x0028 R/W Pin MUX Control Register for Port 9 DCR 0x002C R MCU Device Code Register Table 4.3 Reg. PAMR PBMR P1MR P2MR P3MR P4MR P5MR P6MR P7MR P8MR P9MR DCR MCU Controller Initial values in each mode Mode Mode MODE 2 3,4 5,7 0x0000 0x0000 0x1540 0x0000 0x0000 0x0055 0x0000 0x0000 0x00FF 0x0000 0x0000 0x00FF 0x00FF 0x0000 0x00FF 0x0000 0x0000 0x00FF 0x0000 0x0000 0x000F 0x0000 0x0000 0x03FF 0x0000 0x0000 0x0000 0x0000 0x0000 0x00D4 0x0000 0x0000 0x0000 0x39437092 0x39437092 0x39437092 MODE 6 0x1540 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x39437092 Preliminary 67 MCU controller 4.3.2 PAMR b31 PAMR Flash MCU(HMS39C7092) PINMUX Register Port A Multiplex Register (0x0900_0000 R/W) b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Reserved PA7 PA6 PA5 PA4 PA3 Initial value : depend on operating mode (refer to Table 4.3) PA7 00 : A20 1x : PA7 PA6 00 : A21 1x : PA6 PA5 00 : A22 1x : PA5 PA4 00 : A23 1x : PA4 PA3 00 : TCLKD 1x : PA3 PA2 00 : TCLKC 1x : PA2 PA1 0 : TCLKB PA0 0 : TCLKA PA2 01 01 01 01 01 01 1 1 PA1 PA0 : TIOCB2 : TIOCA2 : TIOCB1 : TIOCA1 : TIOCB0 : TIOCA0 : PA1 : PA2 PBMR b31 PBMR Port B Multiplex Register (0x0900_0004 R/W) b14 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Reserved PB7 PB6 PB5 PB4 PB3 PB2 Initial value : depend on operating mode (refer to Table 4.3) PB7 0 : TCK PB6 0 : TDI PB5 0 : TDO PB4 0 : TMS PB3 00 : /CS4 1x : PB3 PB2 00 : /CS5 1x : PB2 PB1 00 : /CS6 1x : PB1 PB0 00 : /CS7 1x : PB0 PB1 1 1 1 1 01 01 01 01 : PB7 : PB6 : PB5 : PB4 : TIOCB4 : TIOCA4 : TIOCB3 : TIOCA3 PB0 68 Preliminary Flash MCU(HMS39C7092) P1MR b31 P1MR Reserved MCU controller Port 1 Multiplex Register (0x0900_0008 R/W) b8 b7 P17 b6 P16 b5 P15 b4 P14 b3 P13 1 1 1 1 1 1 1 1 b2 P12 : P17 : P16 : P15 : P14 : P13 : P12 : P11 : P10 b1 P11 b0 P10 Initial value : depend on operating mode (refer to Table 4.3) P17 0 : A7 P16 0 : A6 P15 0 : A5 P14 0 : A4 P13 0 : A3 P12 0 : A2 P11 0 : A1 P10 0 : A0 P2MR b31 P2MR Port B Multiplex Register (0x0900_000C R/W) b8 Reserved b7 P27 b6 P26 b5 P25 b4 P24 b3 P23 1 1 1 1 1 1 1 1 b2 P22 : P27 : P26 : P25 : P24 : P23 : P22 : P21 : P20 b1 P21 b0 P20 Initial value : depend on operating mode (refer to Table 4.3) P27 0 : A15 P26 0 : A14 P25 0 : A13 P24 0 : A12 P23 0 : A11 P22 0 : A10 P21 0 : A9 P20 0 : A8 P3MR b31 P3MR Port 3 Multiplex Register (0x0900_0010 R/W) b8 b7 b6 b5 b4 P34 b3 P33 1 1 1 1 1 1 1 1 b2 P32 : P37 : P36 : P35 : P34 : P33 : P32 : P31 : P30 b1 P31 b0 P30 Reserved P37 P36 P35 Initial value : depend on operating mode (refer to Table 4.3) P37 0 : D8 P36 0 : D9 P35 0 : D10 P34 0 : D11 P33 0 : D12 P32 0 : D13 P31 0 : D14 P30 0 : D15 Preliminary 69 MCU controller P4MR b31 P4MR Reserved Flash MCU(HMS39C7092) Port 4 Multiplex Register (0x0900_0014 R/W) b8 b7 P47 b6 P46 b5 P45 b4 P44 b3 P43 1 1 1 1 1 1 1 1 b2 P42 : P47 : P46 : P45 : P44 : P43 : P42 : P41 : P40 b1 P41 b0 P40 Initial value : depend on operating mode (refer to Table 4.3) P47 0 : D7 P46 0 : D6 P45 0 : D5 P44 0 : D4 P43 0 : D3 P42 0 : D2 P41 0 : D1 P40 0 : D0 P5MR b31 P5MR Port 5 Multiplex Register (0x0900_0018 R/W) b4 Reserved Initial value : depend on operating mode (refer to Table 4.3) P53 0 : A19 P52 0 : A18 P51 0 : A17 P50 0 : A16 b3 P53 1 1 1 1 b2 P52 : P53 : P52 : P51 : P50 b1 P51 b0 P50 P6MR b31 P6MR Port 6 Multiplex Register (0x0900_001C R/W) b10 b9 b8 b7 b6 b5 b4 P62 1 1 1 1 1 01 01 1 b3 b2 P61 : P66 : P65 : P64 : P63 : P67 : P62 : P61 : P60 b1 b0 P60 Reserved P66 P65 P64 P63 P67 Initial value : depend on operating mode (refer to Table 4.3) P66 0 : /LWR P65 0 : /HWR P64 0 : /RD P63 0 : /AS P67 0 : BCLK P62 00 : /BACK 1x : Reserved P61 00 : /BREQ 1x : Reserved P60 0 : /WAIT 70 Preliminary Flash MCU(HMS39C7092) P7MR b31 P7MR Reserved MCU controller Port 7 Multiplex Register (0x0900_0020 R/W) b9 b8 P77 b7 b6 P76 b5 b4 P74 b3 P73 01 01 1 1 1 1 1 b2 P72 : /IRQ7 : /IRQ6 : P74 : P73 : P72 : P71 : P70 b1 P71 b0 P70 Initial value : depend on operating mode (refer to Table 4.3) P77 00 : TIOCB5 1x : P77 P76 00 : TIOCA5 1x : P76 P74 0 : AN4 P73 0 : AN3 P72 0 : AN2 P71 0 : AN1 P70 0 : AN0 P8MR b31 P8MR Port 8 Multiplex Register (0x0900_0024 R/W) b8 b7 b6 b5 b4 P82 1 01 01 01 1 b3 b2 P81 : P84 : /IRQ3 : /IRQ2 : /IRQ1 : P80 b1 b0 P80 Reserved P84 P83 Initial value : depend on operating mode (refer to Table 4.3) P84 0 : /CS0 P83 00 : /CS1 1x : P83 P82 00 : /CS2 1x : P82 P81 00 : /CS3 1x : P81 P80 0 : /IRQ0 P9MR b31 P9MR Port 9 Multiplex Register (0x0900_0028 R/W) b11 b10 b9 b8 b7 b6 b5 b4 b3 P92 1 01 01 01 01 1 1 : P97 : P95 : P94 : P93 : P92 : P91 : P90 b2 b1 P91 b0 P90 Reserved P97 P95 P94 P93 Initial value : depend on operating mode (refer to Table 4.3) P97 0 : /TRST P95 00 : /IRQ5 1x : Reserved P94 00 : /IRQ4 1x : Reserved P93 00 : /RxD1 1x : Reserved P92 00 : /TxD1 1x : Reserved P91 0 : RxD0 P90 0 : TxD0 Preliminary 71 MCU controller 4.3.3 MCU Device Code Register Flash MCU(HMS39C7092) (0x0900_002C Read Only) This Register is read only. Device Code Value is `0x3943_7092' 72 Preliminary Flash MCU(HMS39C7092) Power Management Unit Chapter 5 Power Management Unit Preliminary 73 Power Management Unit 5.1 General Description The PMU block provides: * Clock distribution of all over system * Reset, RUN and Power down modes control Flash MCU(HMS39C7092) CLKIN XTALIN SCLK SCLK_GEN MUX BCLK Internal System Module Clock XCLKOUT TEST MODE PIN MUX XTALOUT MODE[2:0] INTC TIMER WDT UART0,1 ADC 1/2 0 MUX Clock Control Register XnRES RESET Filter WDT_Overflow nFIQ Interrupt nIRQ Interrupt RESET Generator PIN MUX PMU State Machine RES_OUT Internal Blocks RESET Figure 5.1 PMU Block Diagram 74 Preliminary Flash MCU(HMS39C7092) 5.2 5.2.1 Power Management Unit Operation Modes Introduction The PMU is consisted of clock controller and reset controller. User can control internal clocks those are embedded peripherals and main clock of MCU by setting the registers of PMU. The MCU has three reset sources those are external power-on reset, soft-reset of PMU, soft-reset of WDT and overflow reset of WDT. And PMU has status registers that old reset value and PMU status. To improve power management, support for a power-saving mode where bus clocks may be disabled (or dropped to lower clock) is included. The reset and power-down mechanism provides: * Stable power-up sequence * Power On Reset * Soft Reset Additionally a system bus, once operational, benefits from well-defined modes of operation: * RUN * Power-down mode 5.2.2 Reset and Operation Modes A set of four useful states or modes is defined as follows: RESET When it is power-on, watchdog timer overflow, watchdog soft-reset or PMU soft-reset, the MCU is initialized Power on Reset This state should be forced by any on-chip power-on-reset cell or external power-on signal and maintained until bus clock is safe and stable. The POR is forced to be in an asynchronous start-up condition and must be recognized by all master and slave devices to disable output drives (and wait for a valid clock). The MCU is running after 32 clocks end of reset timing that rising edge of reset signal. Soft- Reset of PMU The soft-reset, which may need to apply to allow all soft resetting of the bus for a number of clock cycles. In this reset states the PMU block initializes all the ASB blocks, Bus controller, DRAM Controller, DMA Controller, ARM CPU core, and Arbiter, Decoder. Preliminary 75 Power Management Unit Overflow and Soft-Reset of Watchdog timer Flash MCU(HMS39C7092) The watchdog timer can generate reset signal, when timer overflows or sets the register value. Detailed information are in the watchdog timer manual, please refer to it. PDN - Power-Down Mode When MCU system is in the PDN State, PMU block disables all of the blocks in the ASB and APB, so the power consumption of system is dramatically low. Although MCU is in the power down mode, user can set interrupt controller block working in the power down mode. Wake-up from the PDN Mode. The Wake-up is a temporal state for wake-up from power down state through the interruption. After wake-up state, next state becomes RUN state automatically. WDT_Overflow Reset Power-On Reset RESET Wake-up by Power-On Reset Soft-Reset WDT, PMU Power Down PMU Command Wake-up by Interrupt (nFIQ or nIRQ) RUN Figure 5.2 Reset and Power Management State Machine. 76 Preliminary Flash MCU(HMS39C7092) 5.3 Power Management Unit Register Map Power Management Unit The start address of the PMU(Power Management Unit) is 0x0900_1000. Table 5.1 Register Map Name I/O Offset PMUCR 0x1000 PMUSR 0x1000 PCLKCR MEMSR MEMCR RSTCR 0x1008 0x100C 0x1010 0x1030 of the PMU DIR Description W PMU operation mode controls register. R PMU status register shows the just previous PMU state. R/W Peripheral clock control register. R Memory remap status register. W Memory remap control register W Soft-Reset control register Preliminary 77 Power Management Unit 5.4 Register Description Flash MCU(HMS39C7092) The PMU supplies the clock to all of the blocks in the MCU. The start address of register is 0x0900_1000. PMUCR PMU Control Register (0x0900_1000 Write-Only) b31 - b8 PMUCR Reset 0 b7 b6 Reserved 0 0 0 0 0 0 b5 b4 b3 b2 b1 PD 0 b0 Initial value : 0x-00 PD 11 : Entering the Power down Mode 00 : Clear PMU Status Register This register controls the operation mode of PMU. When power on reset states, register value is initialized by Run State (00). If PMUCR is 3, device enters the PD(Power Down) mode. The other values don't effect. The address of register is 0x0900_1000. PMUST PMU Status Register (0x0900_1000 Read-Only) b31 - b8 PMUST Reset Reserved 0 b5 PMUST 0 b4 b3 b2 b1 PMUST 0 0 b0 Reserved - Initial value : 0x-00 This register holds the previous status and reset state of PMU. The address of register is 0x0900_1000. PMUST (Previous Reset Status bits) 00 - The Power-On reset state (nPOR) 01 - PMU Soft-reset state 10 - WDT Soft-reset state 11 - WDT Overflow-reset state PMUST (PMU Status bits) 00 - Start after Power-On reset 01 - reserved state 10 - reserved state 11 - Start after Power-Down mode 78 Preliminary Flash MCU(HMS39C7092) PCLKCR b31 - b16 Power Management Unit Clock Control Register (0x0900_1008 R/W) b15 b14 b13 b12 b11 b10 WDT_CC 0 0 0 b9 b8 b7 b6 B5 b4 b3 b2 b1 b0 PCLKCR Reserved WU_SEL INTC_CC Reset 0 0 UART_Clk 0 0 0 UART_CC 0 0 TIMER_CC 0 0 0 0 ADC_CC 0 0 Initial value : 0x00000000 The address of register is 0x0900_1008. WU_SEL : Wake-up source interrupt select register 0 - MCU wake-up when nFIQ interrupt occurr 1 - MCU wake-up when nIRQ interrupt occurr INTC_CC : Interrupt controller clock control register 0 - Interrupt controller us e the XIN clock. XIN is not killed at any mode 1 - Interrupt controller use the BCLK of internal Bus clock. The Bus clock is killed when Power-down mode WDT_CC : Clock control register of WDT 000 - BCLK 001 - BCLK/2 010 ~ 111 - Reserved UART_Clk : UART0,1 clocks on-off control register. 00 - UART0,1 clocks ON 01 - UART1 clock ON, UART0 clock OFF 10 - UART1 clock OFF, UART0 clock ON 11 - UART0,1 clocks OFF UART_CC : Clocks Control register of UART. 000 - BCLK 001 - BCLK/2 010 ~ 111 - Reserved TIMER_CC : Clocks Control register of TIMER. 000 - BCLK 001 - BCLK/2 010 ~ 111 - Reserved ADC_CC : Clocks Control register of ADC. Values are same as WDT_CC Preliminary 79 Power Management Unit MEMCR MEMSR Flash MCU(HMS39C7092) Memory map Control Register (0x0900_1010 Write-Only) Memory map Status Register (0x0900_100C Read-Only) b31 - b3 b2 SM 0 b1 On-Flash 0 b0 REMAP 0 MEMCR MEMSR Reset Reserved - Initial value : 0x-0 In write operation, the address of register is 0x0900_1010 and in read operation, the address of register is 0x0900_100C. SM : External bus controller mapping change. 0 - Each nCS0 ~ nCS7 of address space is 16MB size 1 - Each nCS0 ~ nCS7 of address space is 1MB size On-Flash : Re-mapping of Flash start address to 0x0 in MODE 6 and 7. 0 - Default value. 1 - Re-mapping of Flash start address to 0x0 in the memory map. It is valid at MODE 6 and 7. REMAP : Re-map internal SRAM address location. 0 - Default value. 1 - Re-mapping of internal SRAM start address to 0x0 in the memory map. It is used at MODE 2,3,4,5,6 and 7. RSTCR Soft-Reset Control Register (0x0900_1030 R/W) b31 - b1 RSTCR Reset Reserved b0 RSTCR 0 Initial value : 0x-0 RSTCR 1 : Normal reset 0 : Normal This register is used for generating the Soft-reset operation. The MCU is entered in reset state, when this register is set to high, it is cleared automatically at the end of Soft-Reset procedure. The address is 0x0900_1030. 80 Preliminary Flash MCU(HMS39C7092) 5.5 Signal Timing Diagram The PMU signal timing is as shown below. Power Management Unit 5.5.1 Power on Reset CLKIN XnRES 32 clks BnRES Figure 5.3 Power on Reset Timing Diagram 5.5.2 Watch Dog Timer Overflow BCLK WD_OF_IN WD_OF_OUT BnRES 256 clks 512 clks Figure 5.4 Watch Dog Timer Overflow Timing Diagram Preliminary 81 Power Management Unit 5.5.3 Soft-Reset Flash MCU(HMS39C7092) There are two Soft-Reset cases. The first Soft-Reset operation is switched by MAN_RST signal from WDT. Another case is from PMU reset control register. BCLK MAN_RST BnRES Figure 5.5 512 clks Soft Reset (from WDT) Timing Diagram BCLK RSTCR BnRES Figure 5.6 512 clks Soft Reset (from PMU) Timing Diagram 82 Preliminary Flash MCU(HMS39C7092) Interrupt controller Chapter 6 The Interrupt Controller Preliminary 83 Interrupt controller Flash MCU(HMS39C7092) 6.1 About the Interrupt controller The interrupt controller has the following features : * Asynchronous interrupt controller * 8 external interrupt sources * 13 internal interrupt sources * Low interrupts latency * Selection of the active modes of all interrupts source inputs (Level or Edge trigger) * Mask-able for each interrupt source and output signal * Selection of the output paths (IRQ or FIQ for each interrupt source) Source Mask Control IRQ IRQ IRQ IRQ IRQ IRQ source0 source1 source2 source3 source4 source5 Trigger Mode Control Polarity Control Direction Control Status Control FIQ Request Control FIQ Mask nFIQ High/ Low, Rising/ Falling Control Mask Control Edge/ Level Control FIQ or IRQ IRQ IRQ Mask nIRQ IRQ source15 IRQ source16 IRQ source17 IRQ source18 IRQ source19 IRQ source20 21 21 21 Clear Control 21 21 21 Figure 6.1 Interrupt Control Flow Diagram 84 Preliminary Flash MCU(HMS39C7092) 6.1.1 Interrupt sources Interrupt controller The interrupt controller provides interface between multiple interrupt sources and the processor. The interrupt controller supports internal and external interrupt sources. Internally there are 1 peripheral interrupt sources. Externally there are 8 interrupt 1 sources. Therefore certain interrupt bits can be defined for the basic functionality required in any system, while the remaining bits are available for use by other devices in any particular implementation. Table 6.1 Interrupt Controller Default Setting Value Interrupt No. INT0 INT1 INT2 INT3 INT4 INT5 INT6 INT7 INT8 INT9 INT10 INT11 INT12 INT13 INT14 INT15 INT16 INT17 INT18 INT19 INT20 INTERRUPT SOURCES External Interrupt 0 External Interrupt 1 External Interrupt 2 External Interrupt 3 External Interrupt 4 External Interrupt 5 External Interrupt 6 External Interrupt 7 reserved reserved WDT UART0 UART1 ADC Timer 0 Timer 1 Timer 2 Timer 3 Timer 4 Timer 5 Software Interrupt The Users can set the active mode of all interrupt source inputs. The default mode is the falling-edge trigger mode. Any inversion or latching required to providing edge sensitivity must be provided at the generating source of the interrupt. No hardware priority scheme or any form of interrupt vectoring is provided, but the priority can be determined using FIQ mask regis ter and IRQ mask register under software control. FIQ mask register and IRQ mask register are also provided to generate an interrupt under software control. Typically these registers may be used to determine either a FIQ interrupt or an IRQ interrupt. 6.1.2 Interrupt Control The interrupt controller provides the interrupt source status and the interrupt request status. The interrupt mask registers are used to determine whether an active interrupt source should generate an interrupt request to the processor or not. A logic-level HIGH in the interrupt mask register indicates that the interrupt source is masked and then doesn`t generate a request. FIQ mask register and IRQ mask register indicate whether the interrupt source causes a processor interrupt or not. Preliminary 85 Interrupt controller Flash MCU(HMS39C7092) The interrupt modes are configurable by interrupt trigger mode register and interrupt trigger polarity register. And Interrupt direction register indicates whether each interrupt source drives IRQ or FIQ. The FIQ and IRQ status register is used to reflect the status of all channels set to produce an FIQ interrupt or IRQ interrupt. And the status registers are cleared by writing `1' to the status clear register in the edge trigger mode only. Bit 20 is used as a software interrupt source. When source mask control register bit 20 is HIGH, an interrupt request occurs. To disable the software interrupt, Source Mask Control Register bit 20 should be Low. Software interrupt source input is fixed active HIGH and level sensitive. 86 Preliminary Flash MCU(HMS39C7092) 6.2 Interrupt Controller Registers Interrupt controller The start address of the interrupt controller is 0x0900_1200. The offset of any particular register from the start address is fixed. The following registers are provided for both FIQ and IRQ interrupt controllers: Table 6.2 Memory Map of the Interrupt Controller REG. I/O OFFSET Dir Description 0x1200 R/W Global Mask Register GMR TMR 0x1204 R/W Trigger Mode Register TPR 0x1208 R/W Trigger Polarity Register IDR 0x120C R/W Interrupt Direction Register FSR 0x1210 R FIQ Status Register ISR 0x1214 R IRQ Status Register FMR 0x1218 R/W FIQ Mask Register IMR 0x121C R/W IRQ Mask Register ISCR 0x1220 W Interrupt Status Clear Register GMR Global Mask Register (0x0900_1200 R/W) b31 - b25 b24b23b22b21b20b19b18b17b16b15b14b13b12b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 GMR Reset Reserved 0000000 I24 I23 I22 I21 I20 I19 I18 I17 I16 I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Initial value : 0x01FFFFF Bit field I0-I24 1 : Mask 0 : Unmask The interrupt mask register is used to mask the interrupt input sources and defines which active sources will generate an interrupt request to the processor. If certain bits within the interrupt controller are not implemented, the corresponding bits in the interrupt mask register must be masked. A bit value 0 indicates that the interrupt is unmasked and will allow an interrupt request to reach the processor. A bit value 1 indicates that the interrupt is masked. Once a bit is masked, the corresponding bit in the status register is cleared. On reset, all interrupt input-sources are masked. TMR Trigger Mode Register (0x0900_1204 R/W) b31 - b25 b24b23b22b21b20b19b18b17b16b15b14b13b12b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 TMR Reset Reserved 0000000 I24 I23 I22 I21 I20 I19 I18 I17 I16 I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Initial value : 0x0100000 Bit field I0-I24 1 : Level Trigger Mode 0 : Edge Trigger Mode The interrupt trigger mode register is used to configure the interrupts with the interrupt trigger polarity register. Each interrupt can be configured to level or edge triggered. A bit value 0 indicates that the interrupt is configured to edge triggered and a bit value 1 indicates that the interrupt is configured to level triggered. On reset, all interrupt input sources are configured to edge triggered. Preliminary 87 Interrupt controller TPR Trigger Polarity Register (0x0900_1208 R/W) Flash MCU(HMS39C7092) b31 - b25 b24b23b22b21b20b19b18b17b16b15b14b13b12b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 TPR Reset Reserved 0000000 I24 I23 I22 I21 I20 I19 I18 I17 I16 I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Initial value : 0x01000000 Bit field I0-I24 1 : High/Rising Edge 0 : Low/Falling Edge The interrupt trigger polarity register is used to configure the interrupts with the interrupt trigger mode register. Each interrupt can be configured to rising/high or falling/low active. A bit value 0 indicates that the interrupt is configured to falling active for edge trigger mode and to low active for level trigger mode. A bit value 1 indicates that the interrupt is configured to rising active for edge trigger mode and to high active for level trigger mode. On reset, all interrupt input sources are configured to falling/low active. Table 6.3 Interrupt Source Trigger Mode DETECTION MODE Falling-Edge (Default) Rising-Edge Low-Level High-Level TMR 0 0 1 1 TPR 0 1 0 1 IDR Interrupt Direction Register (0x0900_120C R/W) b31 - b25 b24b23b22b21b20b19b18b17b16b15b14b13b12b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 IDR Reset Reserved 0000000 I24 I23 I22 I21 I20 I19 I18 I17 I16 I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Initial value : 0x00000000 Bit field I0-I24 1 : Direction to FIQ 0 : Direction to IRQ The interrupt direction register is used to determine whether each interrupt source drives IRQ or FIQ. A bit value 0 indicates that the interrupt is driven to IRQ and a bit value 1 indicates that the interrupt is driven to FIQ. On reset, all interrupt input sources drive IRQ. 88 Preliminary Flash MCU(HMS39C7092) FSR FIQ Status Register (0x0900_1210 Read Only) Interrupt controller b31 - b25 b24b23b22b21b20b19b18b17b16b15b14b13b12b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 FSR Reset Reserved 0000000 I24 I23 I22 I21 I20 I19 I18 I17 I16 I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Initial value : 0x00000000 Bit field I0-I24 1 : FIQ Pending 0 : FIQ Idle The FIQ status register is used to reflect the status of all channels set to produce an FIQ interrupt (IDRn = 1). When an interrupt is set for an FIQ occurring, the corresponding bit is set in FIQ status register. The interrupt handler will examine this register to determine the channel(s) that caused the FIQ interrupt. When the status clear register is written to `1', the corresponding bit is cleared if that channel is configured to edge trigger mode. A HIGH bit indicates that the interrupt is active and will generate an interrupt to the processor. ISR IRQ Status Register (0x0900_1214 Read Only) b31 - b25 b24b23b22b21b20b19b18b17b16b15b14b13b12b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 ISR Reset Reserved 0000000 I24 I23 I22 I21 I20 I19 I18 I17 I16 I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Initial value : 0x00000000 Bit field I0-I24 1 : IRQ Pending 0 : IRQ Idle The IRQ status register is used to reflect the status of all channels set to produce an IRQ interrupt (IDR(i) = 0). When an interrupt is set for an IRQ occurring, the corresponding bit is set in IRQ status register. The interrupt handler will examine this register to determine the channel(s) that caused the IRQ interrupt. When the status clear register is written to `1', the corresponding bit is cleared if that channel is configured to edge trigger mode. A HIGH bit indicates that the interrupt is active and will generate an interrupt to the processor. FMR FIQ Mask Register (0x0900_1218 R/W) b31 - b25 b24b23b22b21b20b19b18b17b16b15b14b13b12b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 FMR Reset Reserved 0000000 I24 I23 I22 I21 I20 I19 I18 I17 I16 I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Initial value : 0x00000000 Bit field I0-I24 1 : Disable FIQ 0 : Enable FIQ The FIQ request mask register is used to mask the request to generate an interrupt to a processor. If certain bits within the interrupt controller are not implemented, the corresponding bits in the FIQ request mask register must be masked. A bit value 0 indicates that the interrupt is unmasked and will allow an interrupt request to reach the processor. A bit value 1 indicates that the interrupt is masked. On reset, all FIQ requests are unmasked. Preliminary 89 Interrupt controller IMR IRQ Mask Register (0x0900_121C R/W) Flash MCU(HMS39C7092) b31 - b25 b24b23b22b21b20b19b18b17b16b15b14b13b12b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 IMR Reset Reserved 0000000 I24 I23 I22 I21 I20 I19 I18 I17 I16 I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Initial value : 0x00000000 Bit field I0-I24 1 : Disable IRQ 0 : Enable IRQ The IRQ request mask register is used to mask the request to generate an interrupt to a processor. If certain bits within the interrupt controller are not implemented, the corresponding bits in the IRQ request mask register must be masked. A bit value 0 indicates that the interrupt is unmasked and will allow an interrupt request to reach the processor. A bit value 1 indicates that the interrupt is masked. On reset, all IRQ requests are unmasked. ISCR Interrupt Status Clear Register (0x0900_1220 Write Only) b31 - b25 b24b23b22b21b20b19b18b17b16b15b14b13b12b11 b10 B9 b8 b7 b6 b5 B4 b3 b2 b1 b0 ISCR Reset Reserved 0000000 I24 I23 I22 I21 I20 I19 I18 I17 I16 I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Initial value : 0x00000000 Bit field I0-I24 1 : Clear Interrupt Status 0 : No action The status clear register is used to clear bits in the status register configured to the edge trigger mode. If the channels are configured to the level trigger mode, the corresponding bits in the FIQ status register and the IRQ status register have no effect. This register is cleared when this register is written to `1'. When writing to this register, each data bit that is HIGH causes the corresponding bit in the status register to be cleared. Data bits that are LOW have no effect on the corresponding bit in the status register. Note that the status clear register has an effect on the status register in the edge trigger mode. 90 Preliminary Flash MCU(HMS39C7092) Watchdog Timer Chapter 7 Watchdog Timer Preliminary 91 Watchdog Timer 7.1 General Description The watchdog timer has: Flash MCU(HMS39C7092) * watchdog timer mode and interval timer mode * interrupt signal INT_WDT to interrupt controller in the watchdog timer mode & interval timer mode * output signal PORESET and MNRESET to PMU(Power Management Unit) * eight counter clock sources * selection whether to reset the chip internally or not * two types of reset signal : power-on reset and manual reset System Clock Clock Generation Clock Selection PORST INT_WDT MNRST Reset Control Interrupt Control Bus Interface Internal Signals Control Logic Overflow RSTSR TCNT Module data bus TCNT : Timer Counter (8-bit) TRCR : Timer/Reset Control Register (8-bit) RSTSR : Reset Status Register (2-bit) Clock TRCR Figure 7.1 Watchdog Timer Module Block Diagram 92 Preliminary Flash MCU(HMS39C7092) 7.2 Watchdog Timer Introduction Watchdog Timer The HMS39C7092 has a one-channel watchdog timer(WDT) for monitoring system operations. If a system becomes uncontrolled and the timer counter overflows without being rewritten correctly by the CPU, an reset signal is output to PMU. When this watchdog function is not needed, the WDT can be used as an interval timer. In the interval timer operation, an interval timer interrupt is generated at each counter overflow. The WDT has a clock generator which produces eight counter clock sources. The clock signals are obtained by dividing the frequency of the system clock. Users can select one of eight internal clock sources for input to the WTCNT by CKS2 - CKS0 in the WTCR. Preliminary 93 Watchdog Timer 7.3 Watchdog Timer Operation The Watchdog Timer Mode Flash MCU(HMS39C7092) To use the WDT as a watchdog timer, set the WT/nIT and TMEN bits of the WTCR to 1. Software must prevent WTCNT overflow by rewriting the TCNT value(normally by writing 0x00) before overflow occurs. If the WTCNT fails to be rewritten and overflow due to a system crash or the like, INT_WDT signal and PORESET/MNRESET signal are output. The INT_WDT signal is not output if INTEN is disabled (INTEN = 0). WTCNT value WT/nIT = 1 0xFF 0x00 Time TMEN = 1 0x00 written in WTCNT WTOVF = 1 FAULT and internal reset generated Figure 7.2 Operation in the Watchdog Timer Mode If the RSTEN bit in the WTCR is set to 1, a signal to reset the chip will be generated internally when TCNT overflows. Either a power-on reset or a manual reset can be selected by the RSTSEL bit. 94 Preliminary Flash MCU(HMS39C7092) The Interval Timer Mode Watchdog Timer To use the WDT as an interval timer, clear WT/nIT to 0 and set TMEN to 1. A watchdog timer interrupt (NT_WDT) is generated each time the timer counter I overflows. This function can be used to generate interval timer interrupts at regular intervals. WTCNT value WT/nIT = 0 0xFF 0x00 Time TMEN = 1 ITOVF = 1 WDTINT generated Figure 7.3 Operation in the Interval Timer Mode 7.3.1 Timing of Setting and Clearing the Overflow Flag Timing of setting the overflow flag In the interval timer mode when the WTCNT overflows, the ITOVF flag is set to 1 and watchdog timer interrupt (INT_WDT) is requested. In the watchdog timer mode when the WTCNT overflows, the WTOVF bit of the SR is set to 1 and a WDTOUT signal is output. When RSTEN bit is set to 1, WTCNT overflow enables an internal reset signal to be generated for the entire chip. Timing of clearing the overflow flag When the Reset Status Register (WRSR) is read, the overflow flag is cleared. Preliminary 95 Watchdog Timer 7.4 Watchdog Timer Memory Map Flash MCU(HMS39C7092) The WDT has five registers. They are used to select the internal clock source, switch to the WDT mode, control the reset signal, and test it. The start address of the watchdog timer is fixed to 0x0900_1100 and the offset of any particular register from the base address is fixed. Table 7.1 Memory Map of the Watchdog Timer APB Peripheral Name I/O Offset DIR Description WTCR 0x1100 R/W WDT control. (8-bit) WRSR 0x1104 R WDT Reset status reg. (2-bit) WTCNT 0x1108 R/W WDT Timer counter. (8-bit) 96 Preliminary Flash MCU(HMS39C7092) 7.5 Watchdog Timer Register Descriptions The following registers are provided for watchdog timer: Watchdog Timer WTCR b31 - b8 WTCR Reset Reserved - Watchdog Timer Control Register ( 0x0900_1100 R/W ) b7 INTEN 0 b6 WT/nIT 0 b5 TMEN 0 b4 RSTEN 0 B3 RSTSEL 0 0 b2 b1 CKSEL 0 0 b0 Initial value : 0x-00 CKSEL : Clock select. Select one of eight internal clock sources for input to the WTCNT. 000 - BCLK / 2 001 - BCLK / 8 010 - BCLK / 32 011 - BCLK / 64 100 - BCLK / 256 101 - BCLK / 512 110 - BCLK / 2048 111 - BCLK / 8192 RSTSEL : Reset select register. Select the type of generated internal reset if the WTCNT overflows in the watchdog timer mode. 0 - Power-on reset 1- Manual reset RSTEN : Reset enable register. Select whether to reset the chip internally of not if the WTCNT overflows in the watchdog timer mode. 0 - Disable 1- Enable TMEN : Timer enable register. Enable or disable the timer. 0 - Disable 1- Enable. WT/nIT : Timer mode select register. Select whether to use the WDT as a watchdog timer or interval timer. 0 - Interval timer mode 1- Watchdog timer mode INTEN : Interrupt enable register. Enable or disable the interrupt request, INT_WDT. 0 - Disable 1- Enable 8-bit readable and writable register. The start address of register is 0x0900_1100. The following functions are provided : * Selecting the timer mode * Selecting the internal clock source Preliminary 97 Watchdog Timer Flash MCU(HMS39C7092) * Selecting the reset mode * Setting the timer enable bit * Being enable interrupt request * Being enable reset signal occurrence The clock signals are obtained by dividing the frequency of the system clock. Table 7.2 Internal Counter Clock Sources (SYSCLK = 40 MHz) CKSEL CLOCK SOURCE OVERFLOW INTERVAL 000 SYSCLK / 2 12.8 us 001 SYSCLK / 8 51.2 us 010 SYSCLK / 32 204.8 us 011 SYSCLK / 64 409.6 us 100 SYSCLK / 256 1.64 ms 101 SYSCLK / 512 3.28 ms 110 SYSCLK / 2048 13.11 ms 111 SYSCLK / 8192 52.43 ms WRSR WRSR Reset Reset Status Register ( 0x0900_1104 Read-Only ) b31 - b2 Reserved b1 ITOVF 0 b0 WTOVF 0 Initial value : 0x-0 1 : Overflowed 0 : Normal WTOVF : Watchdog timer overflow flag. Indicates that the WTCNT has overflowed in the watchdog timer mode. ITOVF : Interval timer overflow flag. Indicates that the WTCNT has overflowed in the watchdog timer mode. Two-bit read only register. The WRSR indicates whether WTCNT is overflowed or not. The WRSR is initialized to 0x0 by the reset signal, nB_RES. Bit 0 (WTOVF) indicates that the WTCNT has overflowed in the watchdog timer mode. Bit 1 (ITOVF) indicates that the WTCNT has overflowed in the interval timer mode. 98 Preliminary Flash MCU(HMS39C7092) WTCNT WTCNT Reset Watchdog Timer Watchdog Timer Counter ( 0x0900_1108 R/W ) b31 - b8 Reserved b7 I7 0 b6 I6 0 b5 I5 0 b4 I4 0 b3 I3 0 b2 I2 0 b1 I1 0 b0 I0 0 Initial value : 0x-00 Bit field I0-I7 8-bit readable and writable upcounter. When the timer is enabled, the timer counter starts counting pulse of the selected clock source. When the value of the WTCNT changes from 0xFF-0x00(overflows), a watchdog timer overflow signal is generated in the both timer modes. The WTCNT is initialized to 0x00 by a power-reset (nB_RES). Preliminary 99 Watchdog Timer 7.6 7.6.1 Flash MCU(HMS39C7092) Examples of Register Setting Interval Timer Mode WTCNT = 0x00 WTCR = 0xA0 SCLK MAIN-CLK WTCNT WRSR WTCR FE 2' b00 FF 00 01 2' b10 10 11 12 2' b00 0xA0 13 14 0 xA0 WDTINT Read RSTSR PORESET `0' MNRESET OVERFLOW ` 0 Figure 7.4 Interrupt Clear in the Interval Timer Mode 100 Preliminary Flash MCU(HMS39C7092) 7.6.2 Watchdog Timer Mode with Internal Reset Disable WTCNT = 0x00 (normally) WTCR = 0xE0 Watchdog Timer XIN MAIN -CLK WTCNT WDSR WDCR FE 2' b00 0xE0 FF 00 2' b01 01 10 11 12 2' 00 0xE0 13 14 WDTINT Read RSTSR Register PORESET ` 0' MNRESET OVERFLOW ` 0 Figure 7.5 Interrupt Clear in the Watchdog Timer Mode with Reset Disable Preliminary 101 Watchdog Timer 7.6.3 Watchdog Timer Mode with Power-on Reset WTCNT = 0x00 WTCR = 0xF0 Flash MCU(HMS39C7092) XIN MAIN -CLK WTCNT WDSR WDCR FE 2' b00 0xF0 FF 00 2' b01 0xF0 01 10 11 12 00 2' b00 WDTINT ` 0 Reset PORESET MNRESET OVERFLOW ` 0 Figure 7.6 Interrupt Clear in the Watchdog Timer Mode with Power-on Reset 102 Preliminary Flash MCU(HMS39C7092) 7.6.4 Watchdog Timer Mode with Manual Reset WTCNT = 0x00 WTCR = 0xF8 Watchdog Timer XIN MAIN-CLK WTCNT FE FF 00 01 10 11 12 13 14 WDSR 2' b00 2' b01 2' 00 WDCR 0xF8 ` 0 0xF8 WDTINT PORESET `' 0 MNRESET OVERFLOW Figure 7.7 Interrupt Clear in the Watchdog Timer Mode with Manual Reset Preliminary 103 Watchdog Timer Flash MCU(HMS39C7092) 104 Preliminary Flash MCU(HMS39C7092) General Purpose Timer Chapter 8 The General Purpose Timer Preliminary 105 General Purpose Timer 8.1 About the General Purpose Timer Unit Flash MCU(HMS39C7092) The general-purpose timer unit has: * Six channels with 16bit counter * 12 different pulse outputs and 12 different pulse inputs * Independent function with 12 general registers * Compare match waveform output function * Input capture function * Counter-clearing function at compare match or input capture mode * Synchronizing mode * PWM mode * 18 interrupt sources * Selectable 4 internal clock sources and 4 external clock sources TCLKA - TCLKD PCLK TIOCA0 - TIOCA5 TIOCB0 - TIOCB5 Clock Generation Clock Selection TINT0 - TINT5 Control TSTARTR 16-bit timer channel0 16-bit timer channel1 16-bit timer channel2 16-bit timer channel3 16-bit timer channel4 16-bit timer channel5 TSYNR Bus Interface Internal data bus TPWMR Module data bus Figure 8.1 General-purpose Timer Unit Module Block Diagram 106 Preliminary Flash MCU(HMS39C7092) 8.1.1 General Purpose Timer Unit Introduction General Purpose Timer The HMS39C7092 has a general-purpose timer unit (GPTU) with six channels of 16bit timer. There are two counter operation modes: a free running mode and a periodic mode. And each channel has independent operating modes. There are common functions for each channel: counter operation, input capture, compare match, PWM, and synchronized clear and write. It is possible to select one of eight counter clock sources for all channels. * Internal clock : counting at falling edge BCLK / 2 BCLK / 4 BCLK / 16 BCLK / 64 * External clock: counting at falling edge. There are five particular operation mode which can be configured respectively. The operation modes are described below. * Free Running Mode * Compare Match Mode * Input Capture Mode * Synchronized Clear and Write Mode * PWM(Pulse Width Modulation) Mode And there are four kinds of counter clear sources which can be selected by user's setting. * None : never clear until overflow for free running mode * GRA match or TPA input capture * GRB match or TPB input capture * Synchronous clear Preliminary 107 General Purpose Timer 8.2 8.2.1 Flash MCU(HMS39C7092) General Purpose Timer Unit Memory Map Register Assignment The base address of the general-purpose timer unit is 0x0900_1300 and the offset of any particular register from the base address is fixed. Table 8.1 Timer Global Control Register Map I/O DESCRIPTION REG. DIR. OFFSET TSTARTR 0x1300 R/W Timer Start Register TSYNCR 0x1304 R/W Timer Sync. Register TPWMR 0x1308 R/W Timer PWM Mode Register 0x130C W (test only) 0x1310 R (test only) 0x1314 W (test only) 0x1318 R (test only) Table 8.2 Timer Channel Control Register Map I/O DESCRIPTION REG. DIR. OFFSET TCR0 0x1320 R/W Timer 0 Control Register TIOCR0 0x1324 R/W Timer 0 I/O Control Register TIER0 0x1328 R/W Timer 0 Interrupt Enable Register TSR0 0x132C R Timer 0 Interrupt Status Register TCNT0 0x1330 R/W Timer 0 Counter Register GRA0 0x1334 R/W Timer 0 General Register A GRB0 0x1338 R/W Timer 0 General Register B GP Timer Unit has consists of six unit timer channels and each address starts at following address Table 8.3 Timer Channel Starting Address Timer No. Timer 0 Timer 1 Timer 2 Timer 3 Timer 4 Timer 5 Starting Offsets 0x1320 0x1340 0x1360 0x1380 0x13A0 0x13D0 108 Preliminary Flash MCU(HMS39C7092) 8.2.2 General Purpose Timer Unit Register Descriptions General Purpose Timer The base address of the general-purpose timer unit is 0x0900_1300. The following registers are provided for general purpose ti mer unit : 8.2.2.1 TSTARTR b31 TSTARTR Reset Reserved - Timer Global Control Registers Timer Start Register (0x0900_1300 R/W) b8 b7 res b6 res b5 STR5 0 b4 STR4 0 b3 STR3 0 b2 STR2 0 b1 STR1 0 b0 STR0 0 1 1 Initial value : 0xXXXXXXC0 STRn 1 : Start Timer Channel n 0 : Stop Timer Channel n 8-bit readable and writable register that starts and stops the counter of each channel. TSYNCR b31 TSYNCR Reset Timer Sync. Register (0x0900_1304 R/W) b8 Reserved b7 res b6 res b5 SYNC5 0 b4 SYNC4 0 b3 SYNC3 0 b2 SYNC2 0 b1 SYNC1 0 b0 SYNC0 0 1 1 Initial value : 0xXXXXXXC0 SYNCn 1 : Operate Synchronously with other sync. channel 0 : Independent Counting 8-bit readable and writable register that selects timer synchronizing mode for each channel. TPWMR b31 TPWMR Reset Reserved - Timer PWM Mode Register (0x0900_1308 R/W) b8 b7 res b6 res b5 PWM5 0 b4 PWM4 0 b3 PWM3 0 b2 PWM2 0 b1 PWM1 0 b0 PWM0 0 1 1 Initial value : 0xXXXXXXC0 PWMn 1 : PWM Mode 0 : Counter Mode 8-bit readable and writable registers that select the PWM mode for each channel. Preliminary 109 General Purpose Timer 8.2.2.2 TCR0 Timer Channel Control Registers Timer 0 Control Register (0x0900_1320 R/W) Flash MCU(HMS39C7092) 0x1340 for Timer 1,0x1360 for Timer 2, 0x1380 for Timer 3, 0x13A0 for Timer 4, 0x13D0 for Timer 5 b31 TCR0 Reset Reserved - b8 b7 res b6 CCLR 00 b5 b4 res 1 b3 res 1 b2 b1 TPSC 000 b0 1 Initial value : 0xXXXXXX98 CCLR Select the Counter clear condition 00 : not cleared (free-running mode) 01 : cleared by GRA compare match or input capture (periodic mode) 10 : cleared by GRB compare match or input capture (periodic mode) 11 : cleared in synchronization with other sync. timer TPSC Select the Count clock Source 000 : BCLK/2 001 : BCLK/4 010 : BCLK/16 011 : BCLK/64 100 : Ext ClkA 101 : Ext ClkB 110 : Ext ClkC 111 : Ext ClkD 8-bit readable and writable register for each channel that selects the timer counter clock source and the counter clear source. 110 Preliminary Flash MCU(HMS39C7092) TIOCR0 Timer 0 I/O Control Register (0x0900_1324 R/W) General Purpose Timer 0x1344 for Timer 1,0x1364 for Timer 2, 0x1384 for Timer 3, 0x13A4 for Timer 4, 0x13D4 for Timer 5 b31 TIOCR0 Reset Reserved - b8 b7 res b6 b5 IOB 00 b4 b3 res b2 b1 IOA 000 b0 1 Initial value : 0xXXXXXX88 1 1 IOB Select GRB Function 000 : compare match with pin output disable 001 : 0 output at GRB compare match 010 : 1 output at GRB compare match 011 : toggle output at GRB compare match 100 : GRB captures the rising edge of input 101 : GRB captures the falling edge of input 110 : GRB captures both edge of input 111 : Don't care IOA Select GRA Function 000 : compare match with pin output disable 001 : 0 output at GRA compare match 010 : 1 output at GRA compare match 011 : toggle output at GRA compare match 100 : GRA captures the rising edge of input 101 : GRA captures the falling edge of input 110 : GRA captures both edge of input 111 : Don't care 8-bit readable and writable register that selects the output compare or input capture function for GRA and GRB, and selects the function of the TIOCAn and TIOCBn pins. TIOCRn controls the GRA and GRB. Preliminary 111 General Purpose Timer TIER0 Flash MCU(HMS39C7092) Timer 0 Interrupt Enable Register (0x0900_1328 R/W) 0x1348 for Timer 1,0x1368 for Timer 2, 0x1388 for Timer 3, 0x13A8 for Timer 4, 0x13D8 for Timer 5 b31 TIER0 Reset Reserved - b8 b7 Res b6 res b5 res 1 b4 res 1 b3 res 1 b2 OVFIE 0 b1 MCIBE 0 b0 MCIAE 0 1 1 Initial value : 0xXXXXXXF8 OVFIE MCIBE MCIAE 0 : Disable Overflow Interrupt 1 : Enable Overflow Interrupt 0 : Disable GRB Match or GRB capture Interrupt 1 : Enable GRB Match or GRB capture Interrupt 0 : Disable GRA Match or GRA capture Interrupt 1 : Enable GRA Match or GRA capture Interrupt 8-bit readable and writable register that controls the enabling/disabling of overflow interrupt request and the general register compare match/input capture interrupt requests. TIERn controls the interrupt enable/disable. TSR0 Timer 0 Status Register (0x0900_132C Read Only) 0x134C for Timer 1,0x136C for Timer 2, 0x138C for Timer 3, 0x13AC for Timer 4, 0x13DC for Timer 5 b31 TSR0 Reset Reserved - b8 b7 res b6 res b5 res 1 b4 res 1 b3 res 1 b2 OVFI 0 b1 MCIB 0 b0 MCIA 0 1 1 Initial value : 0xXXXXXXF8 OVFI MCIB MCIA 0 : no overflow occurs 1 : Overflow occurs 0 : no GRB Match or Capture occurs 1 : GRB Match or Capture occurs 0 : no GRA Match or Capture occurs 1 : GRA Match or Capture occurs 8-bit readable register contains the flags that indicate TCNT overflow and GRA/GRB compare match or input capture. These flags are interrupt sources. 112 Preliminary Flash MCU(HMS39C7092) TCNT0 Timer 0 Counter (0x0900_1330 R/W) General Purpose Timer 0x1350 for Timer 1,0x1370 for Timer 2, 0x1390 for Timer 3, 0x13B0 for Timer 4, 0x13E0 for Timer 5 b31 TCNT0 Reset Reserved - b16 B15 b14 b13 b12 b11 b10 b9 b8 B7 b6 b5 b4 b3 b2 b1 b0 TCNT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Initial value : 0xXXXX0000 TCNT 16bit Counter Value 16-bit readable and writable counter. The clock source is selected by TCR of each channel. TCNT is cleared to 0x0000 by compare match with the corresponding GRA or GRB, or by input capture to GRA or GRB. When TCNT is overflow, OVFI in the TSR is set to `1'. General Register A,B 16-bit readable and writable register. There are 2 general registers for each channel (total 12). Each general register can function as either an output compare register or an input capture register by setting it in the TIOCR. GRA0 General Register A (0x0900_1334 R/W) 0x1354 for Timer 1,0x1374 for Timer 2, 0x1394 for Timer 3, 0x13B4 for Timer 4, 0x13E4 for Timer 5 b31 GRA0 Reset Reserved - b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 GRA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Initial value : 0xXXXX0000 GRA GRB0 General Register B (0x0900_1338 R/W) 16bit Compare Match A Value 0x1358 for Timer 1,0x1378 for Timer 2, 0x1398 for Timer 3, 0x13B8 for Timer 4, 0x13E8 for Timer 5 b31 GRB0 Reset Reserved - b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 GRB 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Initial value : 0xXXXX0000 GRB 16bit Compare Match B Value Preliminary 113 General Purpose Timer 8.3 General Purpose Timer Unit Operation Flash MCU(HMS39C7092) There are five particular operation mode which can be configured respectively. The operation modes are described below. * * * * * Free Running Mode Compare Match Mode Input Capture Mode Synchronized Clear and Write Mode PWM(Pulse Width Modulation) Mode 114 Preliminary Flash MCU(HMS39C7092) 8.3.1 Free Running Mode General Purpose Timer A reset of the counters for channels 0 - 5 leaves them all in the free-running mode. When a corresponding bit in the TSR is set to 1, the corresponding timer counter operates as a free-running counter and begins to increment. When the count wraps round from 0xFFFF - 0x0000, the overflow flag (OVFI) in the timer status register (TSR) is set to 1. If the OVFIE bit in the timer's corresponding interrupt enable register (TIER) is set to 1, the CPU will be asked for an interrupt. After the TCNT overflows, counting continues from 0x0000. Figure 8.2 shows an example of freerunning counting. Periodic counter operation is obtained for a given channel's TCNT by selecting compare match as a TCNT clear source. (Set the GRA or GRB for period setting to output compare register and select counter clear upon compare match using the CCLR1 and CCLR0 bits of the timer control register (TCR). After setting, the TCNT begins incrementing as a periodic counter when the corresponding bit of TSTARTR is set to 1. When the count matches GRA or GRB, the MCIA/MCIB bit in the TSR is set to 1 and the counter is automatically cleared to 0x0000. If the MCIAE/MCIBE bit of the corresponding TIER is set to 1 at this point, the CPU will be asked for an interrupt. After the compare match, TCNT continues counting from 0x0000. Figure 8.3 shows an example of periodic counting. TCNT value 0xFFFF 0x0000 Time STR0-STR4 OVF Figure 8.2 Free-Running Counter Operation Preliminary 115 General Purpose Timer Flash MCU(HMS39C7092) TCNT value GR Counter cleared by GR compare match 0x0000 Time STR0-STR4 OVF Figure 8.3 Periodic Counter Operation 116 Preliminary Flash MCU(HMS39C7092) 8.3.2 Compare Match Mode General Purpose Timer Each channel has 2 general registers and user can read or write from/to the registers. If user wrote some values to general register, and the counter reached that value, the channel generates interrupt and external output by user's setting. The output value can be '1', '0', or toggle value. The counter can be cleared by user's setting when the match with general register i s detected. TCNT value 0xFFFF GRB GRA Time TIOCB Does not change Does not change 1 output TIOCA Does not change Does not change 0 output Figure 8.4 Example of 0 Output/1 Output Preliminary 117 General Purpose Timer Flash MCU(HMS39C7092) TCNT value GRB Counter cleared at GRB compare match GRA Time TIOCB Toggle output Toggle output TIOCA Figure 8.5 Example of Toggle Output CK TCNT input clock TCNT N N+1 GR Compare match signal TIOCA TIOCB N Figure 8.6 Compare Match Signal Output Timing 118 Preliminary Flash MCU(HMS39C7092) 8.3.3 Input Capture Mode General Purpose Timer When set to input capture mode, At the rising/falling edge of either capture input TIOCA or TIOCB, the counter value is transferred to GRA or GRB respectively. Also setting the MCIAE or MCIBE in TIER the interrupt can be generated by the external capture event . If CCR field in TCR is appropriately set, The counter can be cleared when the edge of TIOCA or TIOCA is detected. TCNT value 0x0180 0x0160 Counter cleared by TIOCB input (falling edge) 0x0005 0x0000 TIOCB Time TIOCA GRA 0x0005 0x0160 GRB 0x0180 Figure 8.7 Input Capture Operation Preliminary 119 General Purpose Timer 8.3.4 Synchronized Clear and Write Mode Flash MCU(HMS39C7092) When some channels are set to synchronization mode, and one of them is cleared by compare match or input capture, the other channels can be cleared simultaneously. When some channels are set to synchronization mode and user would write any value to one of them, the other channels can be written with same value simultaneously. TCNT0-TCNT2 value GRB0 GRB1 GRA0 GRB2 GRA1 GRA2 Synchronized clear on GRB0 compare match Time TIOCA0 TIOCA1 TIOCA2 Figure 8.8 Synchronized Operation Example 120 Preliminary Flash MCU(HMS39C7092) 8.3.5 PWM Mode General Purpose Timer The PWM mode is controlled using both the GRA and GRB in pairs. The PWM waveform is output from the TIOCA output pin. The PWM waveform's 1 output timing is set in GRA and the 0 output timing is set in GRB. A PWM waveform with duty cycle between 0% and 100% can be output from the TIOCA pin by having either compare match GRA or GRB be the counter clear source for the timer counter. All five channels can be set to PWM mode. 8.3.5.1 PWM Mode Operation Figure 8.9 illustrates PWM mode operations. When the P WM mode is set, the TIOCA pin becomes the output pin. Output is 1 when the TCNT matches the GRA, and 0 when TCNT matches the GRB. The TCNT can be cleared by compare match with either GRA or GRB. This can be used in both free-running and synchronized operation. TCNT value GRA Counter cleared at GRA compare match GRB Time TIOCA a. Counter cleared by GRA TCNT value GRB Counter cleared at GRB compare match GRA Time TIOCA b. Counter cleared by GRB Figure 8.9 PWM Mode Operation Example 1 Preliminary 121 General Purpose Timer Flash MCU(HMS39C7092) Figure 8.10 shows examples of PWM waveforms output with 0% and 100% duty cycles. A 0% duty waveform can be obtained by setting the counter clear source to GRB and then setting GRA to a larger value than GRB. A 100% duty waveform can be obtained by setting the counter clear source to GRA and then setting GRB to a larger value than GRA TCNT value GRB Counter cleared on compare match B GRA 0x0000 Time TIOCA GRA write a. 0% duty GRA write TCNT value GRB Counter cleared on compare match A GRA 0x0000 Time TIOCA GRB write b. 100% duty GRB write Figure 8.10 PWM Mode Operation Example 2 122 Preliminary Flash MCU(HMS39C7092) General Purpose Timer TCNT0 value GRA1 GRB1 GRB2 GRB3 Synchronized clear on GRA1 compare match Time TIOCA1 TIOCA2 TIOCA3 Figure 8.11 Reset-Synchronized PWM Mode Operation Example Reset-Synchronized PWM Mode Operation: Figure 8.11 shows an example of operation in the reset-synchronized PWM mode. TCNT1 operates as an upcounter that is cleared to 0x0000 at compare match with GRA1. TCNT2 runs independently and is isolated from GRA2 and GRB2. The PWM waveform outputs toggle at each compare match (GRB1, GRB2, and GRB3 with TCNT1) and when the counter cleared. Preliminary 123 General Purpose Timer Flash MCU(HMS39C7092) 124 Preliminary Flash MCU(HMS39C7092) UART Chapter 9 UART (Universal Asynchronous Receiver/Transmitter) Preliminary 125 UART 9.1 General Description Flash MCU(HMS39C7092) This module is an Universal Asynchronous Receiver/Transmitter(UART) with FIFOs, and is functionally identical to the 16450 on power-up (CHARACTER mode). The 16550 can be put into an alternate mode (FIFO mode) to relieve the CPU of excessive software overhead. In this mode internal FIFOs are activated allowing 16 bytes plus 3 bit of error data per byte in the RCVR FIFO, to be stored in both receive and transmit modes. All the logic is on the chip to minimize the system overhead and maximize system efficiency. The UART performs serial-to-parallel conversion on data characters received from a peripheral device and parallel-to-serial conversion on data characters received from the CPU. The CPU can read the complete status of the UART at any time during the functional operation. Status information includes the type and condition of the transfer operations performed by the UART, as well as any error conditions(parity, overrun, framing, or break interrupt). The UART includes a programmable baud rate generator that is capable of dividing the timing reference clock input by divisors of 1 to 65535 and producing a 16x clock for driving the internal transmitter logic. Provisions are also included to use this 16x clock to drive the receiver logic. In addition to baud rate generate, the UART also include clock divider which divide the input system clock by setting the 8-bit divider register. The UART has a processor-interrupt system. Interrupts can be programmed to the user's requirements, minimizing the computing required to handle the communications link. The general 16450/16550 has MODEM control signals, and thus this module also has a MODEM signals internally, but these signals are concealed. UART_CLK ENUCLK0 ENUCLK1 Prescaler Clock Generation Control Bus Interface UCLK0 UCLK1 I N T_ U A R T [ 1 : 0 ] UART0 UART1 Internal bus Figure 9.1 TOP BLOCK Diagram 126 Preliminary Flash MCU(HMS39C7092) 9.2 Features UART * Capable of running all existing 16450 software. * After reset, all registers are identical to the 16450 register set. * The FIFO mode transmitter and receiver are each buffered with 16 byte FIFO's to reduce the number of interrupts presented to the CPU. * Adds or deletes standard asynchronous communication bits (start, stop, and parity) to or from the serial data. * Hold and shift registers in the 16450 mode eliminate the need for precise synchronization between the CPU and serial data. * Independently controlled transmit, receive, line status and data set interrupts. * Programmable baud generator divides any input clock by 1 to 65535 and generates 16x clock * Input clock divider by setting 8-bit divider register. * Independent receiver clock input. * Fully programmable serial-interface characteristics: 5-, 6-, 7- or 8-bit characters Even, odd, or no-parity bit generation and detection 1-, 1.5- or 2-stop bit generation and detection Baud generation (DC to 256k baud) * False start bit detection. * Complete status reporting capabilities. * Line break generation and detection. * Internal diagnostic capabilities . * Loopback controls for communications link fault isolation * Full prioritized interrupt system controls. 9.3 Signal Description Table 9.1 Signal Descriptions Name RXD0 RXD1 Type I I Description Serial Input. Serial data input from the communications link (peripheral device, MODEM or data set). Serial Input. Serial data input from the communications link (peripheral device, MODEM or data set). Serial Output. Composite serial data output to the communications link (peripheral, MODEM or data set). The SOUT signal is set to the Marking (logic 1) state upon a Master Reset operation. Serial Output. Composite serial data output to the communications link (peripheral, MODEM or data set). The SOUT signal is set to the Marking (logic 1) state upon a Master Reset operation. TXD0 O TXD1 O Preliminary 127 UART 9.4 Internal Block Diagram Flash MCU(HMS39C7092) RECEIVER FIFO SELECT DATA BUS BUFFER RECEIVER BUFFER REGISTER RECEIVER SHIFT REGISTER SIN P_D[7:0] LINE CONTROL REGISTER RECEIVER TIMING & CONTROL P_A[0] P_A[1] P_A[2]] P_SEL P_WRITE P_STB U_CLK nB_RES[0] APB I/F & CONTROL LOGIC DIVISOR LATCH(LS) DIVISOR LATCH(MS) BAUD GENERATOR LINE STATUS REGISTER TRANSMITTER FIFO SELECT TRANSMITTER HOLDING REGISTER TRANSMITTER TIMING & CONTROL TRANSMITTER SHIFT REGISTER SOUT MODEM CONTROL REGISTER MODEM CONTROL LOGIC nRTS nCTS nDTR nDSR nDCD MODEM STATUS REGISTER INTERRUPT ENABLE REGISTER INTERRUPT CONTROL LOGIC nRI INT_UART INTERRUPT ID REGISTER FIFO CONTROL REGISTER Figure 9.2 Internal UART Diagram 128 Preliminary Flash MCU(HMS39C7092) 9.5 Registers Description UART There are two UARTs implemented in the design, the base addresses are 0x0900_1400 in UART0 and 0x0900_1500 in UART1. Table 9.2 UART Register Address Map (0x1500 in UART1) Reg. I/O Dir, Description Name Offset RBR 0x1400 R Receiver Buffer (DLAB = 0) THR 0x1400 W Transmitter Holding (DLAB = 0) IER 0x1404 R/W Interrupt Enable IIR 0x1408 R Interrupt Identification FCR 0x1408 W FIFO Control LCR 0x140C R/W Line Control LTR 0x1410 R/W Loop Test Control LSR 0x1414 R/W Line Status 0x1418 Reserved SCR 0x141C R/W Scratch Register DLL 0x1400 R/W Divisor Latch LSB (DLAB = 1) DLM 0x1404 R/W Divisor Latch MSB (DLAB = 1) CLKCR 0x1420 R.W Clock Control CLKDR 0x1424 R/W Clock Divisor Table 9.3 UART Register Reset Values Reg. Reset Values IER 0x00 IIR 0x01 FCR 0x00 LCR 0x00 LTR 0x00 LSR 0x60 TxD `1' Preliminary 129 UART CLKCR b31 CLKCR Reset Reserved Initial value : 0xXXXXXX00 Flash MCU(HMS39C7092) Clock Control Register (0x1420 R/W) b8 b7 b6 b5 B4 Reserved b3 b2 b1 b0 CKEN 0 CKEN 0: Disable UART Clock 1: Enable UART Clock The system programmer starts and stops the UART clock generator the Clock Control Register (CLKCR). The programmer can also read the contents of the Clock Control Register. The CKEN bit is the start clock bit. When this bit is logic 1, the UART clock is generated from the on-chip clock generator. If this bit is a logic 0 , then the clock generator stop to operate. CLKDR b31 CLKDR Reset Reserved Initial value : 0xXXXXXX00 Clock Divisor Register (0x1424 R/W) b8 b7 b6 b5 b4 CKDIV 00 b3 b2 b1 b0 CKDIV 8-bit UART Clock Divisor Value The UART contains a programmable Clock Generator that is capable of taking any clock input and dividing it by any divisor from 0 to 255. One 8-bit register stores the divisor in a 8-bit binary format. This Divisor Register must be loaded before setting the Clock Control Register to ensure the proper operation of the UART Clock Generator. 130 Preliminary Flash MCU(HMS39C7092) LCR b31 LCR Reset Reserved - UART Line Control Register (0x1400 ReadOnly) b8 b7 DLAB b6 BREAK b5 STICKP 0 b4 PARITY 0 b3 PEN 0 b2 STOPBIT 0 b1 DLEN 00 b0 0 0 Initial value : 0xXXXXXX00 00: 5-bit Data 01: 6-bit Data 10: 7-bit Data 11: 8-bit Data STOPBIT 0: 1 stop bit 1: 1.5/2 stop bits PEN 0: Disable Parity 1: Enable Parity PARITY 0: Odd Parity 1: Even Parity STICKP 0: Stick Parity as `0' 1: Stick Parity as `1' BREAK 0: Nomal Transmission 1: Send Break DLAB 0: Nomal state 1: Divisor Latch Access Mode The system programmer specifies the format of the asynchronous data communications exchange and set the Divisor Latch Access bit (DLAB) via the Line Control Register (LCR). The programmer can also read the contents of the Line Control Register. The read capability simplifies the system programming and eliminates the need for separate storage in system memory of the line characteristics. Table 9.8 Summary of Registers shows the contents of the LCR. Details on each bit are : These two bits specify the number of bits in each transmitted and received serial character. STOPBIT This bit specifies the number of Stop bits transmitted and received in each serial character. If bit 2 is a logic 0, one Stop bit is generated in the transmitted data. If bit 2 is a logic 1 when a 5-bit word length is selected via bits 0 and 1, One and a half Stop bits are generated. If bit 2 is a logic 1 when either a 6-, 7-, or 8-bit word length is selected, two Stop bits are generated. The Receiver checks the first Stop-bit only, regardless of the number of selected Stop bits. PEN This bit is the Parity Enable bit. When bit 3 is a logic 1, a Parity bit is generated (transmit data) or checked (receive data) between the last data word bit and Stop bit of the serial data. (The Parity bit is used to produce an even or odd number of 1s when the data word bits and the Parity bit are summed.) PARITY This bit is the Even Parity Select bit. When bit 3 is a logic 1 and bit 4 is a logic 0, an odd number of logic 1s is transmitted or checked in the data word bits and Parity bit. When bit 3 is a logic 1 and bit 4 is a logic 1, an even number of logic 1s is transmitted or checked. STICKP This bit is the Stick Parity bit. When bits 3, 4, and 5 are logic 1, the Parity bit is transmitted and checked as a logic 0. If bits 3 and 5 are 1 and bit 4 is a logic 0, then the Parity bit is transmitted and checked as a logic 1. If bit 5 DLEN DLEN Preliminary 131 UART BREAK Flash MCU(HMS39C7092) is a logic 0 Stick Parity is disabled. This bit is the Break Control bit. It causes a break condition to be transmitted to the receiving UART. When it is set to a logic 1, the serial output ( TxD) is forced to be the Spacing (logic 0) state. The break is disabled by setting bit 6 to a logic 0. The Break Control bit acts only on TxD and has no effect on the transmitter logic. ** Note : This feature enables the CPU to alert a terminal in a computer communications system. If the following sequence is followed, no erroneous or extraneous characters will be transmitted because of the break. DLAB This bit is the Divisor Latch Access Bit. It must be set to high (logic 1) to access the Divisor Latches of the Baud Generator during a Read or Write operation. It must be set to low (logic 0) to access the Receiver Buffer, the Transmitter Holding Register, or the Interrupt Enable Register. DLL/DLM b31 DLL Reset Divisor Latch Register (0x1400/0x1404 R/W) b8 Reserved Initial value : 0xXXXXXX00 b7 b6 b5 b4 DLL 00 b3 b2 b1 b0 DLL b31 DLM Reset Reserved Initial value : 0xXXXXXX00 b8 b7 b6 b5 Divisor Latch Lower Byte b4 DLM 00 b3 b2 b1 b0 DLM Divisor Latch Upper Byte The UART contains a programmable Baud Generator that is capable of taking any clock input from DC to 8.0 MHz and dividing it by any divisor from 2 to 65535. 4MHz is the highest input clock frequency recommended when the divisor=1. The output frequency of the Baud Generator is 16 x the Baud [divisor # = (frequency input) / (baud rate x 16)]. Two 8-bit latches store the divisor in a 16-bit binary format. These Divisor Latches must be loaded during initialization to ensure the proper operation of the Baud Generator. Upon loading either of the Divisor Latches, a 16-bit Baud counter is immediately loaded. Table 12-5 Baud rates provide decimal divisors to use with crystal frequencies of 1.8432 MHz and 3.6864 MHz. For baud rates of 38400 and below, the error obtained is minimal. The accuracy of the desired baud rate depends on the chosen crystal frequency. Using a divisor of zero is not recommended. 132 Preliminary Flash MCU(HMS39C7092) Table 9.4a Divisor Values for each Baud rate (CLK=1.8432MHz) 1.8432 MHz Desired Decimal Divisor Error Percentage Baud Rate Value 50 2304 75 1536 110 1047 0.026 150 768 300 384 600 192 1200 96 1800 64 2000 58 2400 48 3600 32 4800 24 7200 16 9600 12 19200 6 38400 3 57600 2 115200 1 Table 9.4b Divisor Values for each Baud rate (CLK=3.6864MHz) 3.6864 MHz Desired Decimal Divisor Error Percentage Baud Rate Value 50 4608 110 2094 0.026 300 768 1200 192 2400 96 4800 48 9600 24 19200 12 38400 6 57600 4 115200 2 - UART Preliminary 133 UART LSR b31 LSR Reset Reserved - Flash MCU(HMS39C7092) Line Status Register (0x1414 ReadOnly) b8 b7 FIFOE b6 TEMT b5 THRE 1 b4 BI 0 b3 FE 0 b2 PE 0 b1 OE 0 b0 DR 0 0 1 Initial value : 0xXXXXXX60 DR OE PE FE BI THRE TEMT FIFOE 0: 1: 0: 1: 0: 1: 0: 1: 0: 1: 0: 1: 0: 1: 0: 1: No data received Received Data Ready No overrun error Overrun Error No parity error Parity Error No framing error Framing Error No break detected Break Interrupted THR not empty THR Empty Transmitter not empty Transmitter Empty FIFO is valid FIFO has Invalid data This register provides status information to the CPU concerning the data transfer. Table 5 Summary of Registers shows the contents of the Line Status Register. Details on each bit are : DR This bit is the receiver Data Ready indicator. Bit 0 is set to a logic 1 whenever a complete incoming character has been received and transferred into the Receiver Buffer Register or the FIFO. Bit 0 is reset to a logic 0 by reading all of the data in the Receiver Buffer Register or the FIFO. This bit is the Overrun Error indicator. Bit 1 indicates that data in the Receiver Buffer Register was not read by the CPU before the next character was transferred into the Receiver Buffer Register, thereby destroying the previous character. The OE indicator is set to a logic 1 upon the detection of an overrun condition, and reset whenever the CPU reads the contents of the Line Status Register. If the FIFO mode data continues to fill the FIFO beyond the trigger level, an overrun error will occur only after the FIFO is full and the next character has been completely received in the shift register. OE is indicated to the CPU as soon as it happens. The character in the shift register is overwritten, but it is not transferred to the FIFO. This bit is the Parity Error indicator. Bit 2 indicates that the received data character does not have the correct even or odd parity, as selected by the even-parity-select bit. The PE bit is set to a logic 1 upon the detection of a parity error and is reset to a logic 0 whenever the CPU reads the contents of the Line Status Register. In the FIFO mode this error is associated with the particular character in the FIFO where it applies to. This error is revealed to the CPU when its associated character is at the top of the FIFO. This bit is the Framing Error indicator. Bit 3 indicates that the received character did not have a valid stop bit. Bit 3 is set to a logic 1 whenever the Stop bit following the last data bit or parity bit is detected as a logic 0 bit OE PE FE 134 Preliminary Flash MCU(HMS39C7092) UART BI (Spacing level). The FE indicator is reset whenever the CPU reads the contents of the Line Status Register. In the FIFO mode this error is associated with the particular character in the FIFO where it applies to. This error is revealed to the CPU when its associated character is at the top of the FIFO. The UART will try to resynchronize after a framing error. To do this, it assumes that the framing error was due to the next start bit, so it samples this "start" bit twice and then takes it in the "data". This bit is the Break Interrupt indicator. Bit 4 is set to a logic 1 whenever the received data input is held in the Spacing (logic 0) state for longer than a full word transmission time (that is, the total time of Start bit + data bits + Parity + Stop bits). The BI indicator is reset whenever the CPU reads the contents of the Line Status Register. In the FIFO mode this error is associated with the particular character in the FIFO where it applies to. This error is revealed to the CPU when its associated character is at the top of the FIFO. When break occurs only one zero character is loaded into the FIFO. The next character transfer is enabled after SIN goes to the marking state and receives the next valid start bit. ** Note : Bits 1 through 4 are the error conditions that produce a Receiver Line Status interrupt whenever any of the corresponding conditions is detected and the interrupt is enabled. THRE TEMT FIFOE This bit is the Transmitter Holding Register Empty indicator. Bit 5 indicates that the UART is ready to accept a new character for transmission. In addition, this bit causes the UART to issue an interrupt to the CPU when the Transmit Holding Register Empty Interrupt enable is set to high. The THRE bit is set to a logic 1 when a character is transferred from the Transmitter Holding Register into the Transmitter Shift Register. The bit is reset to logic 0 concurrently with the loading of the Transmitter Holding Register by the CPU. In the FIFO mode this bit is set when the XMIT FIFO is empty; it is cleared when at least 1 byte is written to the XMIT FIFO. This bit is the Transmitter Empty indicator. Bit 6 is set to a logic 1 whenever the Transmitter Holding Register (THR) and the Transmitter Shift Register (TSR) are both empty. It is reset to a logic 0 whenever either the THR or TSR contains a data character. In the FIFO mode this bit is set to one whenever the transmitter FIFO and register are both empty. In the 16450 mode, this is 0. In the FIFO mode, FIFOE is set when there is at least one parity error, framing error or break indication in the FIFO. LSR7 is cleared when the CPU reads the LSR, if there are no subsequent errors in the FIFO. ** Note : The Line Status Register is intended for read operations only. Preliminary 135 UART FCR b31 FCR Reset Reserved - Flash MCU(HMS39C7092) FIFO Control Register (0x1408 WriteOnly) b8 b7 b6 b5 Res 0 b4 Res 0 b3 Res 0 b2 FCR2 0 b1 FCR1 0 b0 FIFOEN 0 FIFODEPTH 00 Initial value : 0xXXXXXX00 0: Disable FIFO 1: Enable Both Tx/Rx FIFO FCR1 0: shift register not cleared 1: Self-clear shift register FCR2 0: shift register not cleared 1: Self-clear shift register FIFODEPTH Receive FIFO Trigger Level 00: 1 Byte 01: 4 Bytes 10: 8 Bytes 11: 14 Bytes This is a write only register at the same location as the IIR (the IIR is a read only register). This register is used to enable the FIFOs, clear the FIFOs and set the RCVR FIFO to trigger level. FIFOEN Writing a 1 to FCR0 enables both the XMIT and RCVR FIFOs. Resetting FCR0 will clear all bytes in both FIFOs. When changing from FIFO Mode to 16C450 Mode and vice versa , data is automatically cleared from the FIFOs. This bit must be a 1 when other FCR bits are written to or they will not be programmed. FCR1 Writing a 1 to FCR1 resets its counter logic to 0. The shift register is not cleared. The 1 that is written to this bit position is self-cleared. FCR2 Writing a 1 to FCR2 resets its counter logic to 0. The shift register is not cleared. The 1 that is written to this bit position is self-cleared. FIFODEPTH These bits are used to set the trigger level for the RCVR FIFO interrupt. FIFOEN 136 Preliminary Flash MCU(HMS39C7092) IIR b31 IIR Reset Reserved - UART Interrupt Identification Register (0x1408 ReadOnly) b8 b7 FIFO b6 b5 Res 0 b4 Res 0 b3 FID 0 b2 IID 00 b1 b0 IPEN 1 00 Initial value : 0xXXXXXX01 IPEN IID/FID FIFO 0: Interrupt Pending 1: No Interrupt pending Interrupt Identification Value (refer Table 9.5) Indicate FIFO mode 00: None-FIFO mode 11: FIFO mode In order to provide minimum software overhead during data character transfers, the UART prioritizes interrupts into four levels and records them in the Interrupt Identification Register. The three levels of interrupt conditions are as follows in order of priority: * Receiver Line Status * Received Data Ready * Transmitter Holding Register Empty When the CPU accesses the IIR, the UART freezes all interrupts and indicates the highest priority pending interrupt to the CPU. While this CPU access occurs, the UART records new interrupts, but does not change its current indication until the access is complete. Table 9.6 Summary of Registers shows the contents of the IIR. Details on each bit are : IPEN This bit can be used in a prioritized interrupt environment to indicate whether an interrupt is pending or not. When bit 0 is a logic 0, an interrupt is pending and the IIR contents may be used as a pointer for the appropriate interrupt service routine. When bit 0 is a logic 1, no interrupt is pending. These two bits of the IIR are used to identify the highest priority interrupt pending as indicated in Table 9.5 Interrupt control functions. In the 16450 mode this bit is 0. In the FIFO mode this bit is set along with bit 2 when a time-out interrupt is pending. These two bits are set when FIFOEN = 1. IID FID FIFO Preliminary 137 UART Table 9.5 Interrupt Control Functions FIFO Interrupt Priority Mode Identification Register Level Only Bit 3 Bit 2 Bit 1 Bit 0 Highest 0 0 0 1 0 1 1 0 Flash MCU(HMS39C7092) Interrupt Set and Reset Functions Interrupt Type None Receiver Line Status Receiver Data Available Character Time-out Indication Interrupt Source None Overrun Error, Parity Error, Framing Error or Break Interrupt Receiver Data Available or Trigger Level Reached Interrupt Reset Control Reading the Line Status Register Second 0 1 0 0 Second 1 1 0 0 Third 0 0 1 0 Transmitter Holding Register Empty MODEM Status Fourth 0 0 0 0 Reading the Receiver Buffer Register or the FIFO drops below the trigger level No Characters have been Reading the Receiver removed from or input to Buffer Register the RCVR FIFO during the last 4 Char. times and there is at least 1 Char. in it during this time Transmitter Holding Reading the IIR Register Register Empty (if it is the source of interrupt) or writing it into the Transmitter Holding Register Clear to Send, Data Set Reading the MODEM Ready, Ring Indicator, or Status Register Data Carrier Detect IEN b31 IEN Reset Interrupt Enable Register (0x1404 R/W) b8 Reserved 0 0 Initial value : 0xXXXXXX00 b7 b6 b5 Res 0 0 0 b4 b3 b2 RLSIE 0 b1 THREIE 0 b0 DRIE 0 DRIE 0: 1: THREIE 0: 1: RLSIE 0: 1: No data received Received Data Ready No overrun error Overrun Error No parity error Parity Error This register enables the five types of UART interrupts. Each interrupt can individually activate the interrupt output signal. It is possible to totally disable the interrupt Enable Register (IER). Similarly, setting bits of the IER register to a logic 1 enable the selected interrupt(s). Disabling an interrupt prevents it from being indicated as active in the IIR and from activating the UART interrupt output signal. All other system functions operate in their normal manners, including the setting of the Line Status Registers. Table 9.6 the Summary of Registers shows the contents of the IER. Details on each bit are : DRIE THREIE This bit enables the Received Data Available Interrupt (and time-out interrupts in the FIFO mode) when it is set to logic 1. This bit enables the Transmitter Holding Register Empty Interrupt when set 138 Preliminary Flash MCU(HMS39C7092) RLSIE UART to logic 1. This bit enables the Receiver Line Status Interrupt when it is set to logic 1. LTR b31 LTR Reset Loop Test Control Register (0x1410 R/W) b8 Reserved b7 B6 Res 0 b5 b4 LBON 0 0 0 b3 b2 Res 0 0 b1 b0 0 0 Initial value : 0xXXXXXX00 LBON 0: Normal Transmission 1: Loopback mode This register controls the interface with the MODEM or data set (or a peripheral device emulating a MODEM). The contents of the MODEM Control Register are indicated in Table 9.6 Summary of Registers, and are described below. LBON This bit provides a local loopback feature for diagnostic testing of the UART. When bit 4 is set to logic 1, the transmitter Serial Output (SOUT) is set to the Marking (logic 1) state. The receiver Serial Input (SIN) is disconnected; the output of the Transmitter Shift Register is "looped back" into the Receiver Shift Register input. The four MODEM Control inputs (NCTS, NDSR, NDCD, and NRI) are disconnected. The two MODEM Control outputs (NDTR and NRTS) and two internal nodes (OUT1 and OUT2) are internally connected to the four MODEM Control inputs and the MODEM Control output pins are forced to be their inactive state (high). On the diagnostic mode, the transmitted data is immediately received. This feature allows the processor to verify the transmit- and received-data paths of the UART. In the diagnostic mode, the receiver and transmitter interrupts are fully operational. SCR b31 SCR Reset Scratch Register (0x141C R/W) b8 Reserved Initial value : 0xXXXXXX00 b7 B6 b5 B4 SCR 00 b3 b2 b1 b0 SCR Scratch Register This 8-bit Read/Write Register does not control the UART in any way. It is intended to be used as a scratchpad register by the programmer to hold data temporarily. Preliminary 139 UART 9.6 9.6.1 Flash MCU(HMS39C7092) UART Operations FIFO Interrupt Mode Operation When the RCVR FIFO and receiver interrupts are enabled (FIFOEN = 1, DRIE = 1), RCVR interrupts occur as follows : The received data available interrupt will be issued to the CPU when the FIFO has reached its programmed trigger level; it will be cleared as soon as the FIFO drops below its programmed trigger level. The IIR receive data available indication also occurs when the FIFO trigger level is reached, and like the interrupt it is cleared when the FIFO drops below the trigger level. The receiver line status interrupt (IIR=0x06), as before, has higher priority than the received data available (IIR=0x04) interrupt. The data ready bit (DR) is set as soon as a character is transferred from the shift register to the RCVR FIFO. It is reset when the FIFO is empty. When RCVR FIFO and receiver interrupts are enabled, RCVR FIFO timeout interrupts occurs as follows : 1. A FIFO timeout interrupt occurs in the following conditions : - at least one character is in the FIFO - the latest serial character received was longer than 4 continuous character times (if 2 stop bits are programmed, the second one is included in this time delay). - the latest CPU read of the FIFO was longer than 4 continuous character times. This will cause a maximum character received to interrupt issued delay of 160 ms at 300 baud with a 12 bit character. 2. Character times are calculated by using the RCLK input for a clock signal (this makes the delay proportional to the baud rate). 3. When a timeout interrupt has occurred, it is cleared and the timer is reset when the CPU reads one character from the RCVR FIFO. 4. When a timeout interrupt has not occurred the timeout timer is reset after a new character is received or after the CPU reads the RCVR FIFO. When the XMIT FIFO and transmitter interrupts are enabled ( IFOEN = 1, F THREIE = 1), XMIT interrupts occur as follows : 1. The transmitter holding register interrupt (IIR=0x02) occurs when the XMIT FIFO is empty; it is cleared as soon as the transmitter holding register is written to. (1 to 16 characters may be written to the XMIT FIFO while this interrupt is serviced or the IIR is read.) 2. The transmitter FIFO empty indications will be delayed 1 character time minus the last stop bit time whenever the following occurs: THRE = 1 and there has not been 140 Preliminary Flash MCU(HMS39C7092) UART at least two bytes at the same time in the transmit FIFO since the last THRE = 1. The first transmitter interrupt affect changing F IFOEN will be immediate if it is enabled. Character timeout and RCVR FIFO trigger level interrupts have the same priority as the current received data available interrupt; XMIT FIFO empty has the same priority as the current transmitter holding register empty interrupt. 9.6.2 FIFO Polled Mode Operation When FIFOEN = 1 resetting, DRIE, THREIE, RLSIE or all to zero puts the UART in the FIFO Polled Mode. Since the RCVR and XMITTER are controlled separately, either one or both can be in the polled mode of operation. Preliminary 141 UART 9.7 Register Summary Summary of Registers Offset 0x00 0x00 0x04 0x08 0x08 0x0C 0x10 0x14 0x18 0x1C 0x00 0x01 0x20 0x24 Dir. Bit 7 Bit 6 Bit 5 Bit Field Bit 4 Bit 3 RBR THR Flash MCU(HMS39C7092) Table 9.6 Reg. Name RBR THR IER IIR FCR LCR LTR LSR SCR DLL DLM CLKCR CLKDR Bit 2 Bit 1 Bit 0 cf. DLAB=0 DLAB=0 R W R/W R FID W FIFODEPTH R/W DLAB BREAK STICKP PARITY PEN LBON R/W R FIFOE TEMT THRE BI FE R/W SCR R/W DLL R/W DLM R/W R/W CLKDIV RLSIE THREIE DRIE IID IPEN FCR2 FCR1 FIFOEN STOPBIT DLEN PE OE DR DLAB=1 DLAB=1 CKEN 142 Preliminary Flash MCU(HMS39C7092) GPIO Chapter 10. GPIO (General Purpose Input Output) Preliminary 143 GPIO 10.1 General Description Flash MCU(HMS39C7092) The GPIO is an APB peripheral which provides 79 bits of programmable input /output divided into 11 ports ; port A, port B, port 1, port 2, port 3, port 4, port 5, port 6, port 7, port 8 and port 9. Each pin is configurable as either input or output except port7 [4:0]. At system reset, port A, 1, 3, 5, 8, 9 set their defaults to input and port B, 2, 4, 6, 7 set their defaults to output. PD[7:0] PA[7:2] APB I/F BnRES PSEL PST B PWRITE Port A Data Reg. Port A Dir. Reg. Port B Data Reg. Port B Dir. Reg. EPA[7:0] PA[7:0] Port A PAOE[7:0] EPB[7:0] PB[7:0] Port B PBOE[7:0] Figure 10.1 GPIO Block Diagram and PADS Connections(example for Port A and Port B) Each port has a data register and a data direction register. The data direction register defines whether each individual pin is an input or an output. The data register is used to read the value of the GPIO pins, both input and output, as well as to set the values of pins that are configured as outputs. 144 Preliminary Flash MCU(HMS39C7092) 10.2 GPIO Registers The following user registers are provided: PnDR* GPIO Port n Data Register. Values written to this read/write register will be input on port A pins if the corresponding data direction bits are set to HIGH (port input). Values read from this register reflect the external states of port n, not necessarily the value should be written to it. All bits are cleared by a system reset. Port n Data Direction Register. Bits set in this read/write register will select the corresponding pins in port n to become an input, clearing a bit sets the pin to output. All bits are cleared by a system reset. PnDDR* *n is: A, B, 1, 2, 3, 4, 5, 6, 7, 8 or 9 10.2.1 Register Memory Map The start address of the GPIO is 0x0900_1600 and the offset of any particular register from the base address is determined. Table 10.1 GPIO Register Memory Map I/O REG. DIR DESCRIPTION OFFSET PADR 0x1600 R/W 8-bit Port A Data register PADDR 0X1604 R/W Port A Data Direction register PBDR 0X1608 R/W 8-bit Port B Data register PBDDR 0X160C R/W Port B Data Direction register P1DR 0X1610 R/W 8-bit Port 1 Data register P1DDR 0X1614 R/W Port 1 Data Direction register P2DR 0X1618 R/W 8-bit Port 2 Data register P2DDR 0X161C R/W Port 2 Data Direction register P3DR 0X1620 R/W 8-bit Port 3 Data register P3DDR 0X1624 R/W Port 3 Data Direction register P4DR 0X1628 R/W 8-bit Port 4 Data register P4DDR 0X162C R/W Port 4 Data Direction register P5DR 0X1630 R/W 4-bit Port 5 Data register P5DDR 0X1634 R/W Port 5 Data Direction register P6DR 0X1638 R/W 8-bit Port 6 Data register P6DDR 0X163C R/W Port 6 Data Direction register P7DR 0X1640 R/W 8-bit Port 7 Data register P7DDR 0X1644 R/W Port 7 Data Direction register P8DR 0X1648 R/W 5-bit Port 8 Data register P8DDR 0X164C R/W Port 8 Data Direction register P9DR 0X1650 R/W 8-bit Port 9 Data register P9DDR 0X1654 R/W Port 9 Data Direction register Preliminary 145 GPIO 10.3.1 Register Description Flash MCU(HMS39C7092) Each GPIO port have their own Data register and Data Direction register. All those ports are not 8-bit register. PnDR Port n Data Register (R/W, n is A,B,1,2,3,4,5,6,7,8 or 9) b31 - b8 b7 D7 0 b6 D6 0 b5 D5 0 b4 D4 0 b3 D3 0 b2 D2 0 b1 D1 0 b0 D0 0 PnDR Reset Reserved - Initial value : 0x-00 Bit field D0-D7 1 : On 0 : OFF PnDDR Port n Data Direction Register (R/W, n is A,B,1,2,3,4,5,6,7,8 or 9) b31 - b8 b7 I7 1 b6 I6 1 b5 I5 1 b4 I4 1 b3 I3 1 b2 I2 1 b1 I1 1 b0 I0 1 PnDDR Reset Reserved - Initial value : 0x-FF Bit field I0-I7 1 : Assign the port as Input 0 : Assign the port as Output 146 Preliminary Flash MCU(HMS39C7092) 10.3 Functional Description All block registers are cleared during power on reset. GPIO This disables the output drivers for port A, 1, 3, 5, 8 and 9 (input as default) and enables the drivers for port B, 2, 4, 6 and 7 (output as default). For each port there is a Data Register and a Data Direction Register. On reads, the Data Register contains the current status of correspondent port pins whether they are configured as input or output. Writing to a Data Register only affects the pins that are configured as outputs. The Data Direction Registers operates in a different manner on each port: * For every port, a "0" in the data direction register indicates the port is defined as an output (default), a "1" in the data direction register indicates the port is defined as an input. Preliminary 147 GPIO Flash MCU(HMS39C7092) 148 Preliminary Flash MCU(HMS39C7092) On-Chip SRAM Chapter 11 On-Chip SRAM Preliminary 149 On-Chip SRAM 11.1 General Description Flash MCU(HMS39C7092) The HMS39C7092 has 4-kbytes of high speed static RAM on-chip. The RAM is connected to the CPU by a 32-bit ASB (Advanced System Bus) bus. The CPU accesses byte data, half-word data, and word data in one cycle, making the RAM useful for rapid data transfer. 11.2 Function Description On-Chip SRAM can read data from SRAM and can write data into SRAM in a single clock cycle through ASB bus. And SRAM is single module which have 32-bit data bus and control lines. The data in the On-chip RAM can always be accessed in one cycle that make the RAM ideal for use as a program area, stack area, or data area, which requires highspeed access. The contents of the on-chip RAM are held in both standby and powerdown modes. Since the on-chip RAM is connected to the CPU by an internal 32-bit data bus, it can be written and read by word access. It can also be written and read by half-word or byte access. Memory area 0x0803_0000 to 0x0803_FFFF is allocated to the on-chip SRAM as default. The memory area of the on-chip SRAM is allocated 0x0000_0000 to 0x0000_0FFF in Remap mode. This Remap mode is entered by setting the REMAP flag in MEM_CR of PMU(see Chapter 5 Power Management Unit for detail). 150 Preliminary Flash MCU(HMS39C7092) On-chip Flash memory Chapter 12 On-chip Flash Memory Preliminary 151 On-chip Flash memory 12.1 General Description Flash MCU(HMS39C7092) The HMS39C7092 has 192-Kbytes of on-chip flash memory. The flash memory is connected to the CPU by a 16-bit data bus. The CPU accesses both half-word and word data in several states depending on the wait register value. The on-chip flash memory booting option is enabled and disabled by setting the mode pins (MD 2 to MD 0) as shown in Table 12.1. 12.2 Features The features of the flash memory are summarized below. * * * * * * * * * Memory organization : 96K x 16 (1.5Mbit) Operating Voltage : dual power 3.0V ~ 3.6V(Vcc), 4.5~5.5V(FTVPPD) Random access time : 90nsec Program time : typ. 100usec/word Erase block size : 32KB x 4, 24KB x 2, 8KB x 2 Block erase time : typ. 1.5sec/32KB (pre program + erase) Multiple block erase command support (maximum 4 blocks) Endurance : Min. 100 cycles Both on-chip (user/boot mode) and on-board (PROM mode) program/erase support * Bi-directional Data IO * Operation current : Standby mode : 10uA * Read/Program/Erase mode : max. 20mA 152 Preliminary Flash MCU(HMS39C7092) Table 12.1 Operating mode MD2 0 0 1 1 1 1 MD1 1 1 0 0 1 1 MD0 0 1 0 1 0 1 Mode mode 2 mode 3 mode 4 mode 5 mode 6 mode 7 On-chip Flash memory Description External 8 -bit data bus and 16-Mbyte address mode External 16-bit data bus and 16-Mbyte address mode Flash memory boot mode with external 16-bit data bus mode Flash memory boot mode(micorocomputer mode) UART booting mode with external 16-bit data bus UART booting mode with microcomputer mode Preliminary 153 On-chip Flash memory 12.3 Block Diagram Flash MCU(HMS39C7092) FTVPPD BCLK BA[31:0] BD[31:0] BSIZE[1:0] MODE[2:0] BnRES Decoder DSEL DSELReg Bus Interface/ Controller Flash Array (96K x 16 bits) [16:0] Wait Control WAITREG BWRITE BWAIT BERROR BLAST Test Logic /Controller Figure 12.1 Block Diagram of Flash Memory 154 Preliminary Flash MCU(HMS39C7092) On-chip Flash memory Table 12.2 Signal description of Figure 12.1(BUS Interface) Name I/O Function BnRES I These signal indicate the reset status of the ASB BCLK I The ASB clock timing all bus transfers DSELREG I When this signal is HIGH, it indicates that the Flash Memory configuration Internal registers are selected. (When BA[31:0] is set to FMI Region, 0x09000200~0x090002ff, of Memory Map) DSEL I When this signal is HIGH, it indicates that the Flash Memory Array address is selected. (When BA[31:0] is set to Flash Memory Region of Memory Map.) BWRITE I When this signal is HIGH, it indicates a write transfer and when LOW a read. BSIZE[1:0] I These signals indicate the size of the transfer that may be byte, halfword, or word. BA[31:0] I System address bus. BA[[31:17] is used for selection between Internal Register Block and Flash Memory. BA[16:0] is used for selection of Specific Internal Register or Flash Memory Address. BD[31:0] I/O Bi-directional system data bus. BWAIT O Wait slave response signal. It is driven to phase 1 when Flash Memory Read operation is selected. It is asserted while the Flash Memory Read operation is uncompleted. BERROR O When BEEOR is HIGH, a transfer error has occurred. When BERROR is LOW, then the transfer is successful BLAST O When BLAST is HIGH, the system decoder must allow sufficient time for address decoding. When BLAST is LOW, the next transfer may continue a burst sequence. MODE I These signals are directly connected to external pins(MD 2 ~ MD 0), and [2:0] represent operating mode at table12.1 FTVPPD In It is external power that is used to flash memory program and directly Connected to external pin at all operating mode. Preliminary 155 On-chip Flash memory 12.4 Flash Memory Register Description Flash MCU(HMS39C7092) The registers used to control the on-chip flash memory when enabled are shown in Table 12.3. The base address of the flash memory register(FMU_base) is 0x0900_0200. Table 12.3 Flash Memory Registers Reg. WAITREG ADDREG DATAREG CONTREG EBR STATPWR TESTR I/O Offset 0x0200 0x0204 0x0208 0x020C 0x0210 0x0214 0x0218 Dir. R/W R/W R/W R/W R/W R/W R/W Description Wait Register Address Register Data Register Control Register Erase Block Select Register Status & Power Register Test Register Initial Value 0x000F 0x0000 0xFFFF 0x0000 0x0000 0x0000 0x0400 WAITREG Bit Wait Control Register (WAITREG) 7 W7 6 W6 0 R/W 5 W5 0 R/W 4 W4 0 R/W 3 W3 1 R/W 2 W2 1 R/W 1 W1 1 R/W 0 W0 1 R/W Initial Value Read/Write 0 R/W WAITREG is an 8-bit register used for bus access wait time control. The initial value is 0xF. Once Read command is executed, the next command execution is delayed for the number of bus clocks(BCLK) that the WAITREG is set. So, Flash Memory Read Operation is performed during the time of WAITREG value * period of BCLK. For the successful execution of Flash Memory Read Operation without interruption, this time must be longer then a Flash Memory Access time(TACC). The typical value of WAITREG using 33 MHz-clock input is 03H, which means that the delay time is 90nsec. 156 Preliminary Flash MCU(HMS39C7092) ADDREG Bit 16 A16 Init. Val. RD/WR 0 R/W 15 A15 0 R/W On-chip Flash memory Address Register 14 A14 0 R/W 13 A13 0 R/W 12 A12 0 R/W 11 A11 0 R/W 10 A10 0 R/W 9 A9 0 R/W 8 A8 0 R/W 7 A7 0 R/W 6 A6 0 R/W 5 A5 0 R/W 4 A4 0 R/W 3 A3 0 R/W 2 A2 0 R/W 1 A1 0 R/W 0 A0 0 R/W Address of 16-bit word to be programmed or verified is stored in this register in the Program mode(including Pre-Program) and the Verify mode (program/erase verify). In Normal Read Mode, FA[16:0] is passed directly in address decoding block without passing through ADDREG. In Erase Mode, selecting block in `block select register' causes the specified Flash Memory block to be erased. Users can write this register directly at mode1(PROM Mode) by setting FR_SEL signal, and usable address range are 96K x16 bits, 0x00000 ~ 0x17FFF. In this Mode, if FR_SEL[2:0] is `001' and FWEB is rising_edge, FA[16:0] is passed into ADDREG. If FR_SEL[2:0] is `001', FWEB is `1' and FOEB='0', users are able to read 16-bit of ADDREG[16:1] through FD[15:0] in this Mode. In other mode except mode1, ADDRREG are written via decoded value from BA[16:0] of the Flash Memory address write command (not the ADDRREG write) and read directly through ADDRREG read. DATREG Bit 15 D15 Init. Val. RD/WR 1 R/W 14 D14 1 R/W Data Register 13 D13 1 R/W 12 D12 1 R/W 11 D11 1 R/W 10 D10 1 R/W 9 D9 1 R/W 8 D8 1 R/W 7 D7 1 R/W 6 D6 1 R/W 5 D5 1 R/W 4 D4 1 R/W 3 D3 1 R/W 2 D2 1 R/W 1 D1 1 R/W 0 D0 1 R/W Register for storing data that is programmed to Flash Memory Address of ADDREG value in Program mode. Each bit is corresponded to each cell one by one and if it's 0, cell can be programmed, else not programmed. Flash Memory of HMS39C7092 can be programmed 16 bits at one time. After reset, Data register output value is all reset to 0xFFFF and the other registers are reset to `0'. Users can write this register directly at mode1(PROM Mode). In this Mode, if FR_SEL[2:0] = `001' and FWEB = rising_edge, FD[15:0] is passed into DATAREG. If FR_SEL[2:0] = `010', FWEB = `1' and FOEB='0', users are able to read 16-bit of DATAREG[15:0] through FD[15:0] . In other mode except mode1, DATARREG are written via BD[16:0] of the Flash Memory address write command (not the DATARREG write) and read directly using DATAREG read. Preliminary 157 On-chip Flash memory CONTREG Bit 7 Initial Value Read/Write - Flash MCU(HMS39C7092) Control Register 6 5 ER_VFY 0 R/W 4 PGM_VFY 0 R/W 3 ERSE 0 R/W 2 PGM 0 R/W 1 ER_PWR 0 R/W 0 PGM_PWR 0 R/W CONTREG is an 8-bit register used for flash memory operating mode control. It can be read and written in all modes. It controls transition to state of flash memory array read, program and erase operation, and charge pump operation mode. Table 12.4 shows the function of each bit of Control register. Program process has one modes(PGM) and Verify process has two modes (PGM_VFY,ER_VFY) Table 12.4 Control Register Name PGM_PWR ER_PWR PGM ERSE PGM_VFY ER_VFY Function Program Power Setup (Drain/Positive Gate Pump Enable) Erase Power Setup (Negative/Positive Gate Pump Enable) Program Start bit. Program Pulse Supply to Addressed Cell (Drain/Gate Pulse) Erase Start bit. Erase Pulse Supply to Addressed Block (Gate/Bulk Pulse) Program Verify Read Enable (Positive Gate Pump Enable) Erase Verify Read Enable (Positive Gate Pump Enable) Controlling control bit of Control register in table 12.4 can perform Program/Erase /Verify process. PGM_PWR/ER_PWR sets up the pump before Program and Erase. To make high voltage necessary to program or erase Flash memory address, set the PGM_PWR for program or ER_PWR for erase and wait for the pump setup time. After setting up the pump, set the PGM for program or ERSE for erase to start program or erase. In verify mode, without setting bit0 and bit1, setting one bit corresponds to each verify modes (PGM_VFY,ER_VFY) set up the pump and perform verify read. In Mode1, if FR_SEL[2:0] is `011' and FWEB is rising_edge, FD[7:0] is passed into CONTREG. If FR_SEL[2:0] is `011', FWEB is `1' & FOEB='0', users are able to read 8-bit of CONTREG through FD[7:0] . In other mode except mode1, CONTREG register write and read are both possible. 158 Preliminary Flash MCU(HMS39C7092) EBR Bit 7 SEC7 Initial Value Read/Write 0 R/W On-chip Flash memory Erase Block Select Register 6 SEC6 0 R/W 5 SEC5 0 R/W 4 SEC4 0 R/W 3 SEC3 0 R/W 2 SEC2 0 R/W 1 SEC1 0 R/W 0 SEC0 0 R/W The Bits of this register is used as selector for `Erase block(sector)' and each bit of this register is matched to each erase block(sector). After setting CONTREG for erase, block erase is performed by setting each corresponding block number bit in EBR to 1. Table 12.5 depicts bit-corresponding sector number and the size of sector and their address of lower 18bits. Capable of multiple block erase by setting multiple bits of this register. (Maximum 4 blocks at a time) In Mode1, if FR_SEL[2:0] is `100' & FWEB is rising_edge, FD[7:0] is passed into EBR. If FR_SEL[2:0] is `100', FWEB is `1'& FOEB is '0', users are able to read 8-bit value of EBR[16:1] through FD[7:0] . In other mode except mode1, EBR register write and read are both possible. Table 12.5 Erase Block Register Sector # Sector 0 Sector 1 Sector 2 Sector 3 Sector 4 Sector 5 Sector 6 Sector 7 Sector Size 8KB (4K-word) 8KB 24KB 24KB 32KB 32KB 32KB 32KB Address Range 0x00000 ~ 0x01FFF 0x02000 ~ 0x03FFF 0x04000 ~ 0x0BFFF 0x0B000 ~ 0x0FFFF 0x10000 ~ 0x17FFF 0x18000 ~ 0x1FFFF 0x20000 ~ 0x27FFF 0x28000 ~ 0x2FFFF STATPWR Bit 8 HVEEI Initial Value Read/Write 0 R/W Status & Power Register 7 LVEEI 0 R/W 6 LVCC 0 R/W 5 VEEI[1:0] 00 R/W 4 3 reserved 00 2 1 VPPI[1:0] 00 R/W 0 This is register regulates high voltage pump output voltage and indicates status of pump in Program mode and Erase mode. In the following table, bit[8:6] are status bits to indicate status of pump and bit[5:0] are power control bits to regulate high voltage pump output voltage. Bit[5:0] are read/write register that controls voltage of wordline/ bulk needed in Program, erase and verify mode. In Mode1, if FR_SEL[2:0] is `101' & FWEB is rising_edge, FD[5:0] is passed into STATPWR[5:0] (STATPWR[8:6] are read only). If FR_SEL[2:0] is `101' and FWEB is `1', users are able to read 9 -bit of STATPWR through FD[8:0] . In other mode except mode1, STATPWR write and read are both possible. Preliminary 159 On-chip Flash memory Flash MCU(HMS39C7092) Bit 8 7 6 5,4 3,2 1,0 Table 12.6 Status & Power Register Name Function HVEEI It's 1, when the `ER_PWR' in CONTREG is 1 and VEEI(Negative Gate pump output voltage) is below -7V(i.e. -7.1V) LVEEI It's 1 when VEEI voltage is risen over -1V to discharge. LVCC It's 1 when Pump is running (PGM_PWR=1 or ER_PWR=1) and VDD becomes below 2.9V. VEEI[1:0] These bits define VEEI (Negative Gate Pump output voltage) when the `ER_PWR' of CONTREG is 1. ("00" : -9V, "01" : -10V, "10" : -8V, "11" : -10V) reserved These bits are reserved by future use VPPI[1:0] These bits define VPPI(Positive Gate Pump output voltage) when either PGM_PWR or ER_PWR is 1. These bits also define VPPI value differently as program or erase mode, when one of verify mode enable bits in CONTREG is 1. Program/Erase Mode ("00" : 9V, "01" : 8V, "10" : 10V, "11" : 7V) Verify_Mode ( 00" : 4V, "01" : 5V, "10" : 6V, "11" : 7V) " 160 Preliminary Flash MCU(HMS39C7092) 12.5 On-Board Programming Mode On-chip Flash memory When pins are set to on-board programming mode and a reset-start is executed, the chip enters the on-board programming state in which on-chip flash memory programming, erasing, and verifying can be carried out. There are two operating modes in this - boot mode and user program mode - set by the mode pins. Boot mode is for use when user program mode is not available, such as the first time on-board programming is performed, or if the program activated in user program mode is accidentally erased. 12.5.1 Boot Mode When mode pins are set to 6 or 7 and reset-start is executed, the HMS39C7092 enters the Boot Mode programming state in which on-chip flash memory programming, erasing, verifying can be carried out. There are two operating modes in this mode - mode6 is extended mode, mode7 is one-chip micro-controller mode. This device has Internal ROM area for booting. This ROM area locates in 0x00000000 , when SBM(Serial Boot Mode) = `1' (i.e. boot mode (Mode6 or 7)), and used for Serial Boot when device is reset. If boot mode is used, a flash memory programming control program must be prepared beforehand in the host, and UART channel 0 is to be used. When a reset-start is executed after setting the HMS39C7092 to mode6 or mode7, the boot program in is activated - the bit rate register value determined to 38400 bps(in 33.86MHz), then on-chip UART receives a user program (flash memory programming control program) from off-chip. The received user program is written into RAM (0x08030000 ~ 0x0803FFFF). Figure 12.2 shows a system configuration diagram when using mode6 or mode7, and figure 12.3 show the boot program mode execution procedure. HMS39C7092 Boot ROM TXD Host ARM (PC) RXD SRAM Flash Memory Figure 12.2 System Configuration When Using On-Board Boot Mode Preliminary 161 On-chip Flash memory 1 Flash MCU(HMS39C7092) 1.Set the mode pins to an on-chip flash memory enable mode & programming control program should be prepared beforehand (mode6,7) 2.Start the HMS39C7092 with a reset. 3.Set UART0 input clock(UCLK0) to 3.07818MHz from Source Clock (33.86MHz), and start UCLK0 4.Set Divisor Latch Mode (LCR0 =80h), and set Divisor Latch to 38400bps (DLL0=05h, DLM0 =00h) 5. Set UART0 to 8-bit/1-Stop/NoParity (LCR0=03h) 6.Wait for Receiver (LSR0==1) 7.Get 1byte from Register(RBR) No Set Mode pins to mode6,7 2 Reset-Start UCLK0 Setting (CLKDR=0Bh) & UCLK0 Start (CLKCR=01h) 3 Set Baud Rate to 38400bps (LCR0=80h,DLL0=05h ,DLM0=00h) 4 5 Set UART0 to 8-bit/1-Stop/NoParity (LCR0=03h) Data Ready Buffer Receiver 6 RXRdy(LSR0=1) ? Yes 7 8 No Get 1-byte from RxBuffer 8.Store the user program , which is from RBR, to SRAM and increase SRAM Address pointer by 1 9.If not finished writing to 4Kbyte SRAM, return to 6. Store to SRAM Increase SRAM ptr 10.Branch to SRAM Start address and execute user program (flash memory programming control program) 9 10 RxSize = 4096? Yes Branch to Start of SRAM Figure 12.3 Boot Mode Execution Procedure When boot mode is initiated, the HMS39C7092 measures the low period of the asynchronous communication data transmitted continuously from the host. The UART transmit/receive format should be set as 8-bit data, 1 stop bit, no parity. To ensure correct UART operation, the host s transfer bit rate should be set to 38400 ' bps, and the operating frequency for this process should be 33.86MHz. 162 Preliminary Flash MCU(HMS39C7092) On-chip Flash memory Application example (Boot Mode) 1. Download Application Program Flash Download Algorithm Data Step 1. Set Serial Boot Mode to `1' (flash download algorithm program should be prepared in the host beforehand) Step 2. Reset system Step 3. ARM runs Boot Program in internal ROM. Step 4. Boot program receives flash download algorithm program through UART from Host. Step 5. Store the flash download algorithm program into the internal SRAM. UART Flash ROM ARM CORE BOOT ROM SRAM 2. Run Downloaded Application Program Flash ROM Code Step 6. ARM branches to the start address of the flash download algorithm program. Step 7. The algorithm program gets flash ROM code from host through UART and executes flash ROM Write operation with the code. Step 8. End the flash ROM Write operation and Host changes system mode to Normal. Step 9. Reset Step 10. ARM Execute New Program in the flash ROM. Flash ROM (flash ROM code) UART ARM CORE BOOT ROM SRAM (flash download program) Preliminary 163 On-chip Flash memory 12.5.2 User Program Mode Flash MCU(HMS39C7092) When set to user program mode, the HMS39C7092 can program and erase its flash memory by executing a user program/erase control program. Therefore, on-board reprogramming of the on-chip flash memory can be carried out by providing programming data and program/erase control program at the host, and storing transfer program of a program/erase control program in flash memory area beforehand. To select user program mode, select a mode that enable the on-chip flash memory (mode 4 or 5). Mode4 is extended mode, and mode5 is one-chip micro-controller mode. The flash memory itself cannot be read while being programmed or erased, so the control program that performs program/erase should transferred from external memory to RAM and executed in RAM. Figure 12.4 shows the execution procedure when user program mode is entered during program execution in RAM. 1 Set Mode pins to mode4,5 1.Set the mode pins to an on-chip flash memory enable mode (mode4,5) 2.Start the HMS39C7092 with a reset. 3.Execute transfer program in flash memory. program/erase control program is transferred from host to on-chip RAM through UART. 4. Branch to program/erase control program in RAM. 5.Excute the program/erase control program in RAM. As a result, rewriting of the user application program in flash memory is performed. 6.On completion of rewrite, branch to new user application program 2 Reset-Start 3 Transfer program/erase control program to RAM 4 Branch to Program in RAM 5 Execute program/erase control program in RAM (flash memory rewriting) 6 Execute user application program in flash memory Figure 12.4 User Mode Execution Procedure 164 Preliminary Flash MCU(HMS39C7092) On-chip Flash memory Application example (User Program Mode) 1. Download Application Program Program/erase Control program Transfer program Data Step 1. Set Serial Boot Mode to `1' Boot mode (mode 4 or 5) Step 2. Reset system Step 3. ARM runs Transfer Program in the flash memory, and transfer the program/erase control program to internal SRAM. UART Flash ROM ARM CORE BOOT ROM SRAM 2. Run Downloaded Application Program User application program UART Flash ROM ARM CORE BOOT ROM SRAM Program /erase control program Step 4. ARM branches to the start address of the Program/erase control program in SRAM Step 5. If flash memory has been programmed, Program/erase control program erase flash memory in block Units before program Step 6. Program/erase control program gets user application program from host through UART and executes flash memory program operation with the code in the erased flash memory block. Step 7. End the flash memory program operation and Host changes system mode to Normal. Step 8. Reset Step 9. ARM Execute New Program in the flash ROM. Preliminary 165 On-chip Flash memory 12.6 Flash Memory Programming/Erasing Flash MCU(HMS39C7092) A software method, using the CPU, is employed to program and erase flash memory in the on-board programming modes. There are five flash memory operation modes: pre-program/program mode, post-program mode, erase mode, pre-program/program verify mode, and erase verify mode. The transitions to these modes are made by setting CONTREG register. The flash memory cannot be read while being programmed or erased. T herefore, the program (user program) that controls flash memory program/erase should be located and executed in on-chip RAM or external memory. 12.6.1 Program & Program-Verify Mode When writing data or programs to flash memory, the program flowchart shown in figure 12.5 should be followed. Flash Memory of HMS39C7092 can be programmed 16bits at one time. In Program Verify, the data written in program mode is read to check whether it has been correctly written in the flash memory. If result of verify read at a certain address is not same as the progammed data of this address, progam must be retried to the time when Verify read result and the progammed data are matched. However, if the program/program verify sequence is repeated N times and verify read result is not same as programmed data, it is program fail. 166 Preliminary Flash MCU(HMS39C7092) On-chip Flash memory N=120 CONTREG = 01h Wait for 10uS CONTREG = 05h Wait for 200nS Flash Addr <- ( Pgm Data ) Wait for 5uS CONTREG = 00h Wait for 2uS indexes address Wait for 200nS STATPWR = 002h Wait for 200nS CONTREG = 10h Wait for 3uS Read data CONTREG = 00h STATPWR = 00h Wait for 2uS No No Read Data** = Pgm Data ? Yes Program mode Repeat on same Address Verify mode repeated N times? Yes Program Fail end *Pgm data is the data to be written in flash ** Read data is result of Programmed Flash Addr Figure 12.5 Flash Program & Program Verify Sequence Preliminary 167 On-chip Flash memory Flash MCU(HMS39C7092) 12.6.2 Pre-program & Pre-program Verify Mode This is the first step of flash memory erase algorithm. Pre-program & Pre-program Verify must be done before block erase. The difference between Program and Pre-program is that the purpose of Preprogram is programming not-programmed cell in a certain block that will be erased. Due to Pre-programming before block erase, every cell in the block that will be erased goes to program state , so it is possible to prevent cell from being over-erased after block erase. When Pre-program mode, program address must start at first address of block to be erased, and increase by 2 to the last address of that block. The relation between each erase block and corresponding flash memory address is shown at the Table 12.5 of chapter 12.3. Pre-program needs to do pre-program verify read to ensure that every cell in the block are programmed successfully. The CONTREG setting are the same as program & program verify mode. The Flow of pre-program and pre-program verify is shown at Figure 12.6 168 Preliminary Flash MCU(HMS39C7092) N=120 CONTREG = 01h Wait for 10uS CONTREG = 05h Wait for 200nS Flash Addr* <- 0 Wait for 5uS CONTREG = 00h Wait for 2uS Repeat on same Address indexes address Wait for 200nS STATPWR = 002h Wait for 200nS CONTREG = 10h Wait for 3uS Read data CONTREG = 00h STATPWR = 00h Wait for 2uS No repeated N times ? Yes No On-chip Flash memory Program mode Verify mode Program Fail No Read Data = Pgm Data ? Yes Wait for 200nS Met the end of the block? Yes *At Pre-program , Addr must start at first address of block that will be erased and increase by 2 to the last address of the block. end Figure 12.6 Flash Pre-program & Pre-program Verify Sequence Preliminary 169 On-chip Flash memory Flash MCU(HMS39C7092) 12.6.3 Erase & Erase Verify Mode Flash memory erase operation are performed block by block. To erase flash memory, make a setting for the flash memory area to be erased in erase block register(EBR). If multiple bits of EBR register are set, multiple block are erased at one time. The Maximum number of blocks that can be erased at one time is four. After Erase, it is necessary to do Erase verify read to ensure that every cell in the block are erased successively. When Erase verify read mode, verify address must start at first address of block to be erased, and increase by 2 to the last address of that block. The relation between each erase block and corresponding flash memory address is shown at the table 12.5 of chapter 12.3. If the result of verify read at a certain address is not 0xFFFF, erase must be retried until the result of Verify read is 0xFFFF. However, if the erase/erase verify sequence is repeated N times and the result of verify read is not 0xFFFF, device is erase fail. The Flow of erase & erase verify is shown at Figure 12.7. 170 Preliminary Flash MCU(HMS39C7092) start N=1 CONTREG <= 02h Wait for 10uS Set Erase Block Bit at EBR Wait for 200nS CONTREG <= 0Ah Wait for 1mS STATPWR <= 000h Wait for 200nS CONTREG <= 20h Re-erase N=N+1 Wait for 200nS Flash Addr* <= FFFFh Wait for 10uS Read Flash Addr Yes N < 20 On-chip Flash memory Erase mode Verify mode No Read Data** = FFFFh ? Yes Last Addr of block? Addr=Addr+2 No *At Erase Verify, Addr must start at first address of block that will be erased ,and increase by 2 to the last address of the block. ** Read data is result of verify read at Erased Flash Addr No Yes CONTREG <= 00h Wait for 2uS Erase Fail end Figure 12.7 Flash Erase & Erase Verify Sequence Preliminary 171 On-chip Flash memory 12.6.4 Erase Algorithm Flash MCU(HMS39C7092) When erasing flash memory, the sequence of Figure 12.8 should be followed. It is composed of pre-program & pre-program verify, erase & erase-verify and postprogram to prevent all cells in the erased block from being over-erased. start Pre-program & Pre-program verify Yes Pre-Program Fail No Erase & Erase verify Change block Number Yes Erase Fail? No Yes Another block erase? Fail No end Figure 12.8 Flash Erase Algorithm 172 Preliminary Flash MCU(HMS39C7092) 12.7 Flash Memory PROM Mode On-chip Flash memory The HMS39C7092 has a PROM mode as well as the on-board programming modes for programming and erase flash memory. In PROM mode, the on-chip flash memory can be freely programmed using a PROM writer. 12.7.1 PROM Mode Setting By setting FR_SEL signal, internal register of flash memory are directly write or read through FD[15:0] as table 12.7. When value of FR_SEL[2:0] is set and FWEB = rising_edge, FD[15:0] signals are passed into the register that FR_SEL select. When value of FR_SEL[2:0] is set and FOEB is low, the register's value is read through the FD[15:0]. Table 12.8 shows how the different external pins are set to write and read internal register. Table 12.7 FR_SEL Value for access to internal Register FR_SEL[2:0] 000 001 010 011 100 101 Register Read Read Data ADDREG DATAREG CONTREG EBR STATPWR[8:0] Register Write Reserved ADDREG & DATAREG Reserved CONTREG EBR STATPWR[5:0] Table 12.8 Setting for Register read/write Register Pin Name Mode FRSTB FCEB FWEB FOEB FD[15:0] Read Write High High Low Low High Rising edge Low High Read value output Write Value input FA[16:0] Address input Address input Preliminary 173 On-chip Flash memory 12.7.2 Memory Map Flash MCU(HMS39C7092) The memory map of PROM mode are shown at Table 12.9 At PROM mode, on-chip flas h is 96K x 16 memory. Therefore, In order to access very next 16bit data to the currently accessed address, address should be changed by `1'(not by `2'), Erase operation is performed by sector, and corresponding address of each sector are shown. Table 12.9 Erase Block Register Sector # Sector 0 Sector 1 Sector 2 Sector 3 Sector 4 Sector 5 Sector 6 Sector 7 Sector Size 8KB (4K-word) 8KB 24KB 24KB 32KB 32KB 32KB 32KB FA [16:0] 0x00000 ~ 0x00FFF 0x01000 ~ 0x01FFF 0x02000 ~ 0x04FFF 0x05000 ~ 0x07FFF 0x08000 ~ 0x0BFFF 0x0C000 ~ 0x0FFFF 0x10000 ~ 0x13FFF 0x14000 ~ 0x17FFF 12.7.3 PROM Mode Operation Each flash memory operation, such as program, erase, read are made by writing and reading the flash memory internal register. Table 12.10 shows different flash memory operation and register read/write sequence of each operation. Every operation except for memory normal read and erase, the 1 and 2 'st 'nd cycles are deciding which operation will be performed, and 3'rd cycle is setting flash memory address to be programmed or verified. Therefore, only 3 cycle need to be 'rd repeated if another flash memory address is programmed or verified repeatedly after first address. At Erase operation, 2'nd and 3'rd cycle have to be repeated. At Verify read operation (Pre-Program/program Verify and erase verify), In order to get the result of verify read, it is necessary to execute memory normal read operation after 3'rd cycle. 174 Preliminary Flash MCU(HMS39C7092) On-chip Flash memory Table 12.10 Setting for Flash PROM read/write 1'st Cycle 2'nd Cycle Operation Memory Normal Read Memory Program /Pre-program Memory Post-program Memory Erase Program/Preprogram verify Erase Verify read FR_SEL Mode Address Data FR_SEL Mode Address Data FR_SEL 3'rd Cycle Mode Address Data 000 011 R W RA Dout X 0X0001 011 W X 0X0005 001 W WA Din 011 011 101 W W W X 0X0001 X 0X0002 X 0X0001 011 100 011 W W W X 0X0041 X BN X 0X0010 001 011 001 W W W WA Din X 0X000A RA X 101 W X 0X0000 011 W X 0X0020 001 W RA X < Legend > RA: Read Address WA: Write address Dout: Read data Din: Program data X: don't care R: Read W: Write BN: Erase Block Number(see Table 12.6) 12.7.4 Timing Diagram and AC/DC Characteristics This timing diagram follows the sequence that is shown on Table 12.11. FWEB FRSTB TCEB FCEB TOEB TOEBH FOEB FADDR<16:0> FR_SEL<2:0> XXX TACC RA TR_SEL 000 Dout FD<15:0> Figure 12.9 Timing Diagram of Read Preliminary 175 On-chip Flash memory FRSTB Trst Tpup Flash MCU(HMS39C7092) Tpgm Tpdw FA [16:0] FCEB D o n ' Care A d d r ( X X X X X h ) t Tces Twep WA FWEB FOEB FR_SEL[2:0] 011b T d s Tdh FD [15:0] 0001h 0005h Din 011b 001b 1' t s Cycle 2'n d Cycle 3'rd Cycle Figure 12.10 Timing Diagram of Pre-Program/Program Trst FRSTB FA[16:0] Tces FCEB Twep FWEB Tpuo Tera Tpdw D o n't Care FOEB FR_SEL[2:0] 0 0 1b T d s Tdh FD[15:0] 0002h BN 000Ah 100b 011b 2' nd 3'rd 1' st Cycle Cycle Cycle Figure 12.11 Timing Diagram of Erase < Legend > RA: Read Address WA: Write address Dout: Read data Din: Program data X: don't care R: Read W: Write BN: Erase Block Number(see Table 12.6) 176 Preliminary Flash MCU(HMS39C7092) Trst FRSTB FA[16:0] Tces FCEB Twep FWEB FOEB FR_SEL[2:0] 101b Tds Tdh FD[15:0] 0001h 0010h X 011b 001b RA(Valid) Tvfy On-chip Flash memory Tdout Tpdw 000b Dout 1'st 2'nd 3 'rd Cycle Cycle Cycle Read Cycle Figure 12.12 Timing Diagram of Pre-Program/Program Verify Trst FRSTB FA[16:0] Tces FCEB Tweb FWEB FOEB FR_SEL[2:0] 1 0 1b T d sT d h FD[15:0] 0000 h 0020 h X 0 1 1b 0 0 1b Tvfy Tdout Tpdw RA(Valid) 000b Dout 1' t s 2 'n d C y c l e Cycle 3 'rd Cycle Read Cycle Figure 12.13 Timing Diagram of Erase Verify < Legend > RA: Read Address WA: Write address Dout: Read data Din: Program data X: don't care R: Read W: Write BN: Erase Block Number(see Table 12.6) Preliminary 177 On-chip Flash memory Flash MCU(HMS39C7092) Table 12.11 DC Characteristics - Preliminary ( VDD = 3.3V10%, Vss = 0V, Vss = 0V, FTVPPD = 5V10%, Ta = 25C 10% ) Item Symbol Min Typ Max Unit Test Condition Input high voltage Input low voltage Output high voltage Output low voltage Vcc Reading current Programming Erasing FXTVPPD Programming Current Vih Vil Voh Vol Idd Idd Idd lppd 0.7x VDD -0.5 2.4 ----------- --------20 40 25 10 VDD +0.5 0.3x VDD --0.4 40 80 50 20 V V V V mA mA mA mA Ioh=0.8mA Iol=0.8mA Table 12.12 AC Characteristics - Preliminary (VDD = 3.3V10%, Vss = 0V, Vss = 0V, FXTVPPD = 5V10%, Ta = 25C 10% ) Item CEB output delay time OEB output delay time Output disable delay time R_SEL output delay time Access time Reset Pulse Width Power up time Discharge time(Program,Verify) Discharge time(Erase) Program time CEB Setup time WEB Pulse Width WEB rise time WEB fall time Data Setup time Data Hold time Erase time Verify Setup time Verify data out time Symbol Min Typ Max Unit TCEB TOEB TOEBH TR_SEL TACC Trst Tpup Tpdw ----1 ----300 8 1 10 30 100 100 ----50 50 1 8 2 70 5 2 1 70 500 10 10 20 30 200 200 20 20 150 80 2 10 2 90 10 --2 90 ------- ns ns ns ns ns us us us us us us ns ns ns ns ns ms us us Tpgm Tces Twep Tr Tf Tds Tdh Tera Tvfy Tdout ------30 30 ----2 ----- 178 Preliminary Flash MCU(HMS39C7092) A/D Converter Chapter 13 A/D Converter Preliminary 179 A/D Converter 13.1 Overview Flash MCU(HMS39C7092) The HMS39C7092 has a 10-bit successive-approximations A/D converter with a selection of up to five analog input channels. The A/D converter has multiplexed five input channels. The serial output is configured to interface with standard shift registers. The differential analog voltage input allows for common-mode rejection or offset of the analog zero input voltage value. The voltage reference input can be adjusted to allow encoding any smaller analog voltage span to the full 10bits of resolution. 13.1.1 Features A/D converter features are listed below. l l l l l l l l l 10-bit resolution 5 input channels Selectable analog conversion voltage range: The analog voltage conversion range can be programmed by input of an analog reference voltage at the VREF pin. High-speed conversion: Conversion time: minimum 2us per channel (with 8Mhz ADC clock) Analog input range: GND ~ AVREF Five 10-bit data registers A/D conversion results are transferred for storage into data registers corresponding to the channels. Sample-and-hold function A/D interrupt requested at end of conversion: At the end of A/D conversions, an A/D End Interrupt (ADI) can be requested. A/D Conversion Section AN0 AN1 AN2 AN3 AN4 Mux Auto -zero Comparator 11bit SAR BUS Interface/ Controller Format Converter ADDR0 ADDR1 ADDR2 DA1 DVSS DVDD AVREF AVSS AVDD Clock & Phase Generator DA2 DA3 ACH[0] ACH[1] ACH[2] ACH[3] ACH[4] Reference Ladder & Calibrator AIOSTOP ACLK ADST ADCCR ADDR3 ADDR4 Internal signals ADCSR Figure 13.1 Block Diagram of A/D Converter 180 Preliminary Flash MCU(HMS39C7092) 13.1.2 Pin Configuration A/D Converter Table 13.1 summarizes the A/D converter's input pins. AVDD and AV SS are the power supply for the analog circuits in the A/D converter. VREF is the A/D conversion reference voltage. Table 13.1 A/D Converter Pins Pin Name Function I/O AVDD Input Analog power supply AVSS Input Analog ground AVREF Input Analog reference voltage AN0 Input Analog input channel 0 AN1 Input Analog input channel 1 AN2 Input Analog input channel 2 AN3 Input Analog input channel 3 AN4 Input Analog input channel 4 Preliminary 181 A/D Converter 13.2 A/D Converter Registers Flash MCU(HMS39C7092) The registers used to control the A/D converter when enabled are shown in Table 13.2. The base address of the A/D converter is 0x0900_1700. Table 13.2 Summarizes the A/D converter's registers. I/O Reg.Name R/W Name Offset ADCSR 0x1700 R/W Control & Status Register ADCCR 0x1704 R/W Control Register ADDR0 0x1708 R Data Register 0 ADDR1 0x170C R Data Register 1 ADDR2 0x1710 R Data Register 2 ADDR3 0x1714 R Data Register 3 ADDR4 0x1718 R Data Register 4 Initial Value 0x00 0x1 0x0000 0x0000 0x0000 0x0000 0x0000 13.2.1 ADCSR Bit Register Descriptions AD Control & Status Register (0x0900_1700 R/W) b7 b6 ADST 0 R/W b5 ADIE 0 R/W 0 R/W b4 ACKS 0 R/W 0 R/W b3 b2 b1 ACHS 0 R/W 0 R/W b0 ADCSR Init. Val. RD/WR ADF 0 R/W Initial Value: 0x00 ACHS Channel select (Select the analog input channel) 000 : Analog input channel 0 001 : Analog input channel 1 010 : Analog input channel 2 011 : Analog input channel 3 100 : Analog input channel 4 Clock select (Select the A/D conversion time) 00 : 1/8 times of the ADC input clock (ADCLK) 01 : 1/4 times of the ADC input clock (ADCLK) 10 : 1/2 times of the ADC input clock (ADCLK) 11 : ADC input clock is from the timer block A/D interrupt enable (Enables and disables A/D conversion) 0 : A/D end interrupt request (INT_ADC) is disabled. 1 : A/D end interrupt request (INT_ADC) is enabled. A/D start (Starts or stops A/D conversion) 0 : A/D conversion is stopped 1 : A/D conversion start; ADST is automatically cleared to 0 when conversion end. ACKS ADIE ADST 182 Preliminary Flash MCU(HMS39C7092) ADF A/D Converter A/D end flag (Indicates end of A/D conversion) 0 : [Clearing condition] Read when ADF=1, then write 0 in ADF. 1 : [Setting condition] Automatically set when conversion end ADCSR is the control and status register for AD converter. ACH[2:0] is used for selection of the analog input channel. CKS[1:0] is used for selection of the AD converter input clock. When these signals are `00', the main clock of the A/D converter is 1/8 times of input clock (ADCLK), which is the same cycle with the system operation clock.. When these signals are `01', then the main clock of the A/D converter is 1/4 times of ADCLK. When these signals are`10', then the main clock of the A/D converter is 1/2 times of ADCLK. When these signals are `11', then the main clock of the A/D converter is external clock from Timer block. ADIE bit is interrupt enable signal. When this signal is `0', then A/D converter does not generate the interrupt of the end of A/D conversion. When this signal is `1', then A/D converter generates the end of conversion interrupt. ADST bit indicate the start of A/D conversion. When this signal is `1', the A/D converter start the A/D conversion and remain high during A/D conversion. ADF indicate the end of A/D conversion. When this bit is `1', then A/D converter indicates the end of A/D conversion. This signal is auto-cleared by reading this bit. ADCCR Bit ADCCR Init. Val. RD/WR AD Control Register (0X0900_1704 R/W) b15-b2 Reserved b1 CALEND 0 R b0 AIOSTOP 1 R/W Initial value: 0x01 CALEND bit field: I0-I1 Calibration end (Indicate the calibration end time) 0 : Indicate not end of calibration time. 1 : Indicate the end of calibration time. AIOSTOP Power save mode 0 : A/D converter is normal operation mode 1 : A/D converter is power save mode, so not operate CALEND indicate the end of calibration time (Tcal). This signal is read only. AIOSTOP is used to set the power save mode of A/D converter. When this signal is`0', then A/D converter is entering normal operation mode after calibration time, or power up time. See Figure 13.2 A/D converter operation for detailed timing diagram. Preliminary 183 A/D Converter ADDR0~4 Bit b15 AD9 Init. Val. RD/WR 0 R b14 AD8 0 R Flash MCU(HMS39C7092) A/D Data Register 0 to 4 (0x0900_1708 ~ 0x0900_1718 R) b13 AD7 0 R b12 AD6 0 R b11 AD5 0 R b10 AD4 0 R b9 AD3 0 R b8 AD2 0 R b7 AD1 0 R b6 AD0 0 R b5 Rev 0 R b4 Rev 0 R b3 Rev 0 R B2 Rev 0 R b1 Rev 0 R b0 Rev 0 R Initial value: 0x0000 bit field: I6-I15 AD[9:0] Rev A/D conversion data (10-bit giving an A/D conversion result) Reserved bit 184 Preliminary Flash MCU(HMS39C7092) 13.3 Operation A/D Converter The A/D converter operates by successive approximations with 10-bit resolution. Figure 13.2 show the operation of A/D converter. AIOSTO CALEN Tca l Analog Sn AVREF ADCLK fsample ADI ADS INT_AD Output Data DATAn Tc Conversion Time Figure 13.2 A/D converter Operation Preliminary 185 A/D Converter 13.4 Interrupts Flash MCU(HMS39C7092) The A/D converter generates an interrupt (INT_ADC) at the end of A/D conversion. The INT_ADC interrupt request can be enabled or disabled by the ADIE bit in ADCSR. 186 Preliminary Flash MCU(HMS39C7092) 13.5 Usage Notes When using the A/D converter, note the following points: A/D Converter 1. Analog Input Voltage Range: During A/D conversion, the voltages input to the analog input pins AN n should be in the range AVss ANn VREF. 2. Relationships of AV CC and AV SS to VCC and VSS: AVCC, AVSS , VCC, and VSS should be related as follows: AVSS = VSS. AVCC and AVSS must not be left open, even if the A/D converter is not used. 3. VREF Programming Range: The reference voltage input at the VREF pin should be in the range VREF AVCC. 4. Note on Board Design: In board layout, separate the digital circuits from the analog circuits as much as possible. Particularly avoid layouts in which the signal lines of digital circuits cross or closely approach the signal lines of analog circuits. Induction and other effects may cause the analog circuits to operate incorrectly, or may adversely affect the accuracy of A/D conversion. The analog input signals (AN 0 to AN 4), analog reference voltage (VREF), and analog supply voltage (AVCC) must be separated from digital circuit by the analog ground (AVSS). The analog ground (AV SS) should be connected to a stable digital ground (VSS) at one point on the board. 5. Note on Noise: To prevent damage from surges and other abnormal voltages at the analog input pins (AN 0 to AN 4) and analog reference voltage pin (VREF), connect a protection circuit like the one in figure 13.3 between AV CC and AVSS. The bypass capacitors connected to AVCC and VREF and the filter capacitors connected to AN 0 to AN 4 must be connected to AV SS. 6. A/D Conversion Accuracy Definitions: HMS39C7092 is defined as follows: * Resolution: * Offset error: A/D conversion accuracy in the Digital output code length of A/D converter Deviation from ideal A/D conversion characteristic of analog input voltage required to raise digital output from minimum voltage value 0000000000 to 0000000001 (figure 13.4) Deviation from ideal A.D conversion characteristic of analog input voltage required to raise digital output from 1111111110 to 1111111111 (figure 13.4) * Full-scale error: * Quantization error: Intrinsic error of the A/D converter;1/2 LSB (figure 13.5) * Nonlinearity error: Deviation from ideal A/D conversion characteristic in range from zero volts to full scale, exclusive of offset error, fullscale error, and quantization error. * Absolute accuracy: Deviation of digital value from analog input value, including offset error, full-scale error, quantization error, and nonlinearity error. Preliminary 187 A/D Converter Flash MCU(HMS39C7092) Analog Reference Signal R1 R2 CC AVRE AVS S .C1~C3:10uF .C4~C6:2200pF .DVSS=0V .DVDD=3.3V .AVREF=3.3V . R1,R2 < 1KU CC AVD Analog Input (VIN=GND +0.2~AVRE F-0.2V) AN AN AN AN AN ACL Ceramic Capacitor Charge Capacitor 7.5M Figure 13.3 Example of Analog Input Circuit Digital Output Full-scale error Ideal A/D Conversion characteristic Nonlinearity error Actual conversion characteristic A/D Offset error FS Analog Input voltage Figure 13.4 A/D Converter Accuracy Definitions (1) 188 Preliminary Flash MCU(HMS39C7092) Digital Output Ideal A/D conversion characteristic 111 110 101 100 011 010 001 000 1/8 2/8 3/8 4/8 5/8 6/8 7/8 Quantization error A/D Converter FS Analog Input voltage Figure 13.5 A/D Converter Accuracy Definitions (2) 7. Effect on Absolute Accuracy: Attaching an external capacitor creates a coupling with ground, so if there is noise on the ground line, it may degrade absolute accuracy. The capacitor must be connected to an electrically stable ground, such as AVSS. If a filter circuit is used, be careful of interference with digital signals on the same board, and make sure the circuit does not act as an antenna. Preliminary 189 A/D Converter 13.6 Example AREA ENTRY ldr add mov str loop ldr cmp bne ldr add mov str loop_adf adr and cmp bne ldr and str ldr add ldr END ADDONE, CODE, READONLY Flash MCU(HMS39C7092) r0, r0, r1, r1, =ADC_base r0, #ADCCR #0 [r0] ; Make AOPSTOP to LOW to releas e power down mode, ; then set normal operation mode. r2, [r0] r2, #2 loop r0, r0, r1, r1, =ADC_base r0, #ADCSR #0x40 [r0] ; Check whether CALEND is set to 1 or not. ; (Check it's in the range of calibration time) ; Set the control bit in ADCSR register ; AD conversion start, CKS=1/8 ADCLK, ACH=0ch ;(set ADST, CKS=0, ACH=0) ;check ADF (AD conversion END) r2, [r0] r2, r2, #0x80 r2, #0x80 loop_adf r1, [r0] r1, r1, #0x7f ; Clear ADF to 0 r1, [r0] r0, =ADC_base r0, r0, #ADDR0 r1, [r0] ;read ADDR0 register into R1 register 190 Preliminary Flash MCU(HMS39C7092) Electrical Characteristics Chapter 14 Electrical Characteristics Preliminary 191 Electrical Characteristics 14.1 Absolute Maximum Ratings Flash MCU(HMS39C7092) Table 14.1 lists the absolute maximum ratings(Note1 and 2). Table 14.1 Absolute Maximum Ratings Item - Preliminary Value Symbol Power supply voltage VDD -0.5V to 4.6V DC Input Voltage (except I/O pins) VIN -0.5V to 6.0V DC Output Voltage (Output in high or low state) VOUT -0.5V to VDD+0.5V DC Output Voltage (output in 3-state) VOUT -0.5V to +6.0V Reference Voltage VREF -0.3V to AVDD+0.3 Analog Power supply voltage AVCC -0.3V to 3.6V Analog Input Voltage VAN -0.3V to AVDD+0.3 Storage Temperature range TS -65 to +150C Note1: Absolute maximum continuous ratings are those values which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute -maximum -rated conditions is not implied. Note2: Under transient conditions these ratings may be exceeded as elsewhere in this specification. 14.2 Recommended Operating Conditions: Table 14.2 lists the recommended operating conditions. Table 14.2 Recommended Operating Conditions Symbol Parameter MIN VDD Supply voltage 3.0 VIN Input voltage 0 VOUT Output voltage outputs active 0 VOUT Output voltage outputs disabled 0 VPPD Flash program/erase voltage 4.5 TA Operating free-air temperature 0 - PreliminaryMAX UNIT 3.6 V 5.5 V VDD V 5.5 V 5.5 V 70 C 192 Preliminary Flash MCU(HMS39C7092) 14.3 DC Characteristics Table 14.3 lists the DC characteristics. Table 14.3 DC Characteristics SYM ITEM MIN MAX BOL Input Low Voltage VIL -0.5 0.3XVDD Input High Voltage VIH 0.7XVDD VDD+0.5 VOL 0.4 Output Low Voltage Output High Voltage Input current at maximum voltage VOH II 2.4 1 Electrical Characteristics - PreliminaryUNIT V V V V mA TEST Conditions VDD=3.0V to 3.6V VDD=3.0V to 3.6V VDD=3.0V IOL=0.8mA VDD=3.0V IOH=-0.8mA VDD=3.0V to 3.6V Input=5.5V Table 14.4 lists the IO circuit with pull-ups Table 14.4 IO Circuits with pull-ups Min Current(at PAD = 0V) 3.3V Pull-up Equivalent resistance 30uA 88.3kOhms - PreliminaryMax Current (at PAD = 0V) -146uA 24.7kOhms Table 14.5 lists the IO circuit with pull-downs Table 14.5 IO Circuits with pull-downs Min Current(at PAD = 2.65V) Pull-down 31uA Equivalent 85.5kOhms resistance - PreliminaryMax Current (at PAD = 3.6V) 159uA 22.6kOhms Preliminary 193 Electrical Characteristics 14.4 AC Characteristics Flash MCU(HMS39C7092) Timing measurement conditions is following that Unless otherwise specified: VDD = 3.3V Junction Temperature = 25 degrees C Process = Typical Low voltage input signal input signal rising and falling edges switching time = 0.3ns Clock timing parameters are listed in table 14.6, control signal timing parameters in table 14.7, and bus timing parameters in table 14.8. Table 14.6 Clock Timing Item Clock cycle time Clock pulse low width Clock pulse high width Clock rise time Clock fall time Clock oscillator Settling time at reset Symbol tCYC tCL tCH tCr tCf tOSC1 Min. 20 10 10 20 Max. 1000 10 10 - PreliminaryTest Units Conditions ns Figure 14.3 ns ns ns ns ms Figure 14.1 Table 14.7 Control Signal Timing Item XnRES setup time XnRES pulse width Mode programming setup time Symbol tRESS tRESW tMDS Min. 200 5 200 Max. - - PreliminaryTest Units Conditions ns Figure 14.2 tCYC ns 194 Preliminary Flash MCU(HMS39C7092) Table 14.8 Bus Timing Item Address delay time Address hold time Read strobe d elay time Address strobe delay time Write strobe delay time Strobe delay time Write strobe pulse width 1 Address setup time 1 Read data setup time Read data hold time Write data delay time Write data setup time 1 Write data hold time Read data access time 1 Read data access time 3 Precharge time 1 Precharge time 2 Wait setup time Wait hold time Bus request setup time Bus acknowledge time 1 Bus acknowledge time 2 Bus-floating time Symbol tAD tAH tRSD tASD tWSD tSD tWSW1 tAS1 tRDS tRDH tWDD tWDS1 tWDH tACC1 tACC3 tPCH1 tPCH2 tWTS tWTH tBRQS tBACD1 tBACD2 tBZD Min. 0 20 10 20 0 10 0 20 0 20 5 20 - Electrical Characteristics Max. 20 20 20 20 20 20 40 40 30 30 30 - PreliminaryTest Units Conditions ns Figure 14.3 Figure 14.4 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Figure 14.5 ns ns ns ns Figure 14.6 ns ns ns Preliminary 195 Electrical Characteristics 14.4 AD Conversion characteristics (Preliminary) Flash MCU(HMS39C7092) Table 14.9 lists the operation conditions of the AD Conversion Table 14.9 Operating Parameter Power Supply Analog Input Clock Pulse Width Operating Temperature Conditions of the AD Conversion - PreliminarySymbol Min. Max. Units AVDD 3.0 3.6 V AN GND+0.2 AVREF-0.2 V TPWL 62.5 ns TOP 0 100 C Table 14.10 lists the electrical characteristics of the AD converter Table 14.10 Electrical characteristics of the AD converter - PreliminaryConditions : Analog input frequency FIN=1.26KHz, ADCLK=7.5MHz, AVDD=DVDD=AVREF=3.3V T=25C Symbol Parameter Conditions Min. Typ. Max. Units IDD Normal ADCLK=7.5MHz 2.0 mA Input=AVREF FIN=1.26KHz ramp Power Down ADCLK=7.5MHz 50 uA AN Analog input GND+ AVREF V voltage 0.2 -0.2 Accuracy Resolution 10 bits INL Integral NonADCLK=7.5MHz LSB 2.0 linearity Input=0-AVREF(V) (FIN=1.26KHz) DNL Differential NonADCLK=7.5MHz LSB 1.0 linearity Input=0-AVREF (FIN=1.26KHz ramp) SNR Signal-to-Noise Fsample=500Ksps, 48 54 dB Ratio FIN=1.26KHz SNDR Signal-to-Noise 45 54 dB Distortion Ratio ADCLK 2 4 8 MHz tc Conversion time 2 4 8 us Co Output 20 pF capacitance Rref Reference 10K U resistance AVREF Analog AVDD V Reference Voltage TCAL Power up time Calibration time 22 ms THD Total harmonic 55 60 dB distortion AVDD Analog power 3.0 3.3 3.6 V DVDD Digital power 3.0 3.3 3.6 V FIN Analog input 5 KHz frequency 196 Preliminary Flash MCU(HMS39C7092) 14.5 Operational Timing Electrical Characteristics 14.5.1 Clock Timing Figure. 14.1 shows the settling time of the crystal oscillator. XTALIN VCC XnSTBY tOSC1 XnRES Figure 14.1 The settling time of the crystal oscillator 14.5.2 Reset Timing Figure 14.2 show the reset input timing and reset output timing. XTALIN XnRES tMDS MD2 to MD0 tRESS tRESS tRESW Figure 14.2 Reset Input Timing Preliminary 197 Electrical Characteristics 14.5.3 Bus Timing Flash MCU(HMS39C7092) Figure 14.3 and Figure 14.6 show the timing diagram of the bus controller. T1 tCYC tCH XTALIN tAD A23 to A0 nCSn nAS tAS1 tASD nHWR, nLWR tAS1 tWDD tSD tWSW1 tWDS1 tWDH tPCH1 tAH tCf tCYC tASD tCr tCL T2 tSD tPCH1 Data (write) Figure 14.3 The Write Timing Diagram of the Bus Controller T1 tCYC tCH XTALIN tAD A23 to A0 nCSn nAS tAS1 tASD tACC3 nRD Data (read) tAS1 tACC1 tCf tCYC tASD tACC3 tCr tCL T2 tSD tPCH1 tRSD tPCH2 tRDH Figure 14.4 The Read Timing Diagram of the Bus Controller 198 Preliminary Flash MCU(HMS39C7092) Electrical Characteristics T1 XIN nWAIT nCSn nAS Address Data (Read) nHWR nLWR nRD tWTS T2 Tw Tw Tw T3 tWTH n Valid `1' `1' Figure 14.5 Basic Bus Cycle with External Wait State XIN nBREQ nBACK Address tBRQS tBRQS tBACD1 tBZD tBZD tBACD2 Figure 14.6 Bus Release Mode Timing Preliminary 199 |
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